NCKUEE Faculty Data
Chinese Version
Professor Lih-Yih Chiou
Address
ChiMei Building 3F R95309
Email
TEL
+886-6-2757575 ext.62379
Lab
Low-Power and High Performance VLSI Lab
(R95316/ext.62400-2582)
Background
Educations
2003
Ph.D. in VLSI and Circuit Design, May 2003, Purdue University, School of Electrical and Computer Engineering, West Lafayette, IN
1993
M. S. in Computer Engineering, August 1993, University of Louisiana, Center for Advanced Computer Studies, Lafayette, LA (Formerly University of Southwestern Louisiana, Lafayette, LA)
1988
Bachelor of Engineering, July 1988, National Cheng-Kung University, Department of Electrical Engineering, Tainan, Taiwan
Experiences
2021-present
Director,Academy of Innovative Semiconductor and Suxtainable Manufacturing _integrated circuit design
2020-present
Director, Electrical Laboratories, College of Engineering, NCKU
2020-present
Professor Dept. of Electrical Engineering, National Cheng Kung University, R. O. C.
2009-2020
Associate Professor Dept. of Electrical Engineering, National Cheng Kung University, R. O. C.
2003-2009
Assistant Professor Dept. of Electrical Engineering, National Cheng Kung University, R. O. C.
1998
Summer Intern Lucent Technology, Holmdel, NJ.;Summer
1992-present
Active Member IEEE
Specialities
  • Power-efficient design in both hardware and software
  • Reconfigurable computing
  • CAD for VLSI
Publication
Journal
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  1. Chi Ray Huang, Lih Yih Chiou "An Energy-Efficient Conditional Biasing Write Assist with Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM" IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol.29,No8,pp1586-1590,2021.
  2. Lih-Yih Chiou, Jing-Yu Huang, Chi-Kuan Li, Chen-Chung Tsai "A Reliable Near-Threshold Voltage SRAM-Based PUF Utilizing Weight Detection Technique" VLSI-DAT 2021: 1-4
  3. Lih-Yih Chiou, Tsung-Han Yang, Jian-Tang Syu, Che-Pin Chang, Yeong-Jar Chang: Intelligent Policy Selection for GPU Warp Scheduler. AICAS 2019: 302-303
  4. Lih-Yih Chiou, Chung-Han Wu, Po-Cheng Wei: A Reliable Delay-Based Physical Unclonable Function with Dark-Bit Avoidance. ISCAS 2019: 1-4
  5. Lih-Yih Chiou, Chao-Kai Yang, Che-Pin Chang:A Data-Traffic Aware Dynamic Power Management for General-Purpose Graphics Processing Units. ISCAS 2019: 1-5
  6. Lih-Yih Chiou, Chi-Ray Huang, Chang-Chieh Cheng, Jing-Yu Huang, Wei-Suo Ling:A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs. VLSI-DAT 2019: 1-4
  7. Lih-Yih Chiou and Chi-Ray Huang, “Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit -interleaved ultra-low voltage operation,” IET Circuits, Devices & Systems, Vol. 12, Issue 6, pp.713-719, Nov. 2018.
  8. Liang-Ying Lu and Lih-Yih Chiou, “Temperature Gradient Exploration Method for Determining the Appropriate Number of Cells in Mesh-Based Thermal Analysis,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, accepted.
  9. Liang-Ying Lu, Tsung-Yu Hsieh, Pei-En Weng, Lih-Yih Chiou, "Methodology for Developing Virtual Platforms from Power-aware to Power- and Thermal-aware at Electronic System Level," IET Cyber-Physical Systems: Theory & Applications, accepted.
  10. Tsai-Kan Chien, Lih-Yih Chiou, Chi-Shian Chang, Jing-Yu Huang, Chung-Han Wu, Heng-Yuan Lee, and Shyh-Shyuan Sheu , “Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F2/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM,” IEEE Trans. Circuits and Systems II: Express Briefs, accepted.
  11. Liang-Ying Lu, Lih-Yih Chiou, "Temperature gradient-aware thermal simulator for three-dimensional integrated circuits," IET Computers & Digital Techniques, Vol. 11, Issue 5, pp.190-196, 2017.
  12. Chin-Lung Yang, Chung-Kai Chang, Shuenn-Yuh Lee, Soon-Jyh Chang, Lih-Yih Chiou, "Efficient Four-Coil Wireless Power Transfer for Deep Brain Stimulation," IEEE Transactions on Microwave Theory and Techniques, Vol. 65, Issue 7, pp.2496-2507, 2017.
  13. Tsai-Kan Chien, Lih-Yih Chiou, Shyh-Shyuan Sheu, Jing-Cian Lin, Chang-Chia Lee, Tzu-Kun Ku, Ming-Jinn Tsai, Chih-I Wu, “Low-Power MCU with Embedded ReRAM Buffers as Sensor Hub for IoT Applications,” IEEE J. Emerging and Selected Topics in Circuits and Systems, Vol. 6, No. 2, pp. 247-257, 2016.
  14. Shien-Chun Luo and Lih-Yih Chiou, "A Sub-200-mV Voltage Scalable SRAM with Tolerance of Access Failure by Self-Activated Bitline Sensing," IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 57, No. 6, pp. 440 - 445, 2010. [SCI, EI, IEEE]
  15. Yongtao Wang Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, and Kaushik Roy, "Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering," Journal of Signal Processing Systems, Vol. 58, No. 2, pp.125-137, Feb 2010. [SCI,EI]
  16. Lih-Yih Chiou, Yi-Siou Chen and Chih-Hsien Lee, "System-Level Bus-Based Communication Architecture Exploration Using a Pseudo Parallel Algorithm" IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol.28, No.8, pp 1213-1223, Aug. 2009. [SCI, EI, IEEE]
  17. Lih-Yih Chiou and Shien-Chun Luo, "Energy Efficient Dual Edge Triggered Level Converting Flip Flops with Symmetry in Setup Times and Insensitivity to Output Parasitics," IEEE Transactions on VLSI System, Vol. 17, No.11, pp.1659-1663, Nov. 2009. [SCI, EI, IEEE]
  18. Meng-Fan Chang, Lih-Yih Chiou, and Kuei-Ann Wen, ”Crosstalk-insensitive via-programming ROMs using content-aware design framework”, IEEE Transactions on Circuit and System II, Vol. 53, No. 6, p.p.443-447, June, 2006. [SCI, EI, IEEE]
  19. Meng-Fan Chang, Lih-Yih Chiou, and Kuei-Ann Wen, “A full code-pattern coverage high-speed embedded ROM using dynamic virtual guardian technique”, IEEE J. Solid-State Circuits, vol. 41, no.2, pp 496-506, February 2006. [SCI, EI, IEEE]
  20. Meng-Fan Chang, Lih-Yih Chiou, and Kuei-Ann Wen, “Code-pattern insensitive embedded ROMs using dynamic bitline shielding technique,” IEE Electronics Letters, vol. 41, no. 15, pp 834-835, July, 2005. [SCI,EI,IEEE]
  21. Lih-yih Chiou, Swarup Bhunia and Kaushik Roy, “ Synthesis of Application-Specific Highly Efficient Multi-more Core for Embedded Systems,” ACM Transactions on Embedded Computing Systems, Vol.4, Issue 1, pp.168-188, 2005.
  22. Mark Johnson, Dinesh Somasekhar, Lih-Yih Chiou and Kaushik Roy, “Leakage Control With Efficient Use of Transistor Stacks in Single Threshold CMOS,” IEEE Transaction on VLSI, pp. 1-5, February 2002.[SCI, EI, IEEE]
  23. Lih-Yih Chiou, Khurram Muhammand and Kaushik Roy, “Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications,” VLSI Design, Vol. 12, No. 2,pp.233-243,2001. [EI, IEEE]
  24. A V. Krishnamoorthy, Lih-Yih Chiou, R G. Rozier and O. Kibar, “Concentrator circuit with multiple priority levels,”Electronics Letters, Vol. 36, No. 6,pp. 500-501, 2000. [EI, IEEE]
Conference
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  1. Lih-Yih Chiou, Tsung-Han Yang, Jian-Tang Syu, Che-Pin Chang, Yeong-Jar Chang, "Intelligent Policy Selection for GPU Warp Scheduler, " in Proc. IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
  2. Lih-Yih Chiou, Chi-Ray Huang, Chang-Chieh Cheng, Jing-Yu Huang, Wei-Suo Ling, "A Variation-Tolerant Bitline Leakage Sensing Scheme for Near-Threshold SRAMs, " in Proc. International Symposium on VLSI Design, Automation and Test , 2019
  3. Lih-Yih Chiou, Chung-Han Wu, Po-Cheng Wei, "A Reliable Delay-Based Physical Unclonable Function with Dark-Bit Avoidance, " in Proc. IEEE International Symposium on Circuits and Systems, 2019
  4. Lih-Yih Chiou, Chao-Kai Yang, Che-Pin Chang, "A Data-Traffic Aware Dynamic Power Management for General-Purpose Graphics Processing Units, " in Proc. IEEE International Symposium on Circuits and Systems, 2019
  5. Lih-Yih Chiou, Chun-Hao Chang ,Liang-Ying Lu, Wei-Hsuan Yang ,Yeong-Jar Chang and Juin-Ming Lu ,"Fast Steady-State Thermal Analysis," in Proc. IEEE International SoC Design Conference, 2018
  6. Chi-Ray Huang, Kuan-Lin Wu, Chung-Han Wu and Lih-Yih Chiou, " Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme," in Proc. IEEE International Symposium on Circuits and Systems, 2018.
  7. Tsai-Kan Chien, Lih-Yih Chiou, Yi-Sung Tsou, Shyh-Shyuan Sheu, Pei-Hua Wang, Ming-Jinn Tsai, Chih-I Wu, " Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches," in IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp.1-6, 2017.
  8. Hugo Cruz, Hong-Yi Huang, Ching-Hsing Luo, Lih-Yih Chiou, Shuenn-Yuh Lee, "A novel clock-pulse-width calibration technique for charge redistribution DACs," in IEEE Heterogeneous Systems With Hybrid DRAM & NVM Memory Architecture," in Proc. IEEE Asia Pacific Conference on Circuits and Systems, 2016. (accepted)
  9. Tsai-Kan Chien, Lih-Yih Chiou, Chieh-Wen Cheng, Shyh-Shyuan Sheu, Pei-Hua Wang, Ming-Jinn Tsai, and Chih-I Wu, "Memory Access Algorithm for Low Energy CPU & GPU Heterogeneous Systems With Hybrid DRAM & NVM Memory Architecture," in Proc. IEEE Asia Pacific Conference on Circuits and Systems, 2016. (accepted)
  10. Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, and Jai-Ming Lin, “A Testable and Debuggable Dual-Core System with Thermal-Aware Dynamic Voltage and Frequency Scaling,” in Proc. IEEE Asia and South Pacific Design Automation Conference, pp. 17-18, 2016.
  11. Tsai-Kan Chien, Lih-Yih Chiou, Chang-Chia Lee, Yao-Chun Chuang, Shien-Han Ke, Shyh-Shyuan Sheu, Heng-Yuan Li, Pei-Hua Wang, Tzu-Kun Ku, Ming-Jinn Tsai, and Chih-I Wu, “An Energy-Efficient Nonvolatile Microprocessor Considering Software-Hardware Interaction for Energy Harvesting Applications,” in Proc. International Symposium on VLSI Design, Automation and Test, pp. 1-4, 2016.
  12. Tsai-Kan Chien, Lih-Yih Chiou, Yao-Chun Chuang, Shyh-Shyuan Sheu, Heng-Yuan Li, Pei-Hua Wang, Tzu-Kun Ku, Ming-Jinn Tsai, and Chih-I Wu, “A Low Store Energy and Robust ReRAM-Based Flip-Flop for Normally Off Microprocessors,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 2803-2806, 2016.
  13. Lih-Yih Chiou, Liang-Ying Lu, and Chieh-Yu Lin, “An Effective Matrix Compression Method for GPU-Accelerated Thermal Analysis,” in Proc. International Symposium on VLSI Design, Automation and Test, pp. 1-4, 2015.
  14. Chi-Ray Huang and Lih-Yih Chiou,"A Limited-Contention Cross-Coupled Level Shifter for Energy-Efficient Subthreshold-to-Superthreshold Voltage Conversion," in Proc. IEEE International SoC Design Conference, pp. 142-143, 2014.
  15. Lih-Yih Chiou, Chi-Ray Huang and Ming-Hung Wu, “A Power-Efficient Pulse-based In-situ Timing Error Predictor for PVT-Variation Sensitive Circuits,” in Proc. IEEE International Symposium Circuits and Systems, pp. 1215-1218, 2014
  16. Shien-Chun Luo, Chi-Ray Huang and Lih-Yih Chiou, “An Ultra-Low-Power Adaptive-Body-Bias Control for Subthreshold Circuits,” in Proc. IEEE International Symposium on VLSI Design, Automation & Test, pp. 1-4, 2014.
  17. Lih-Yih Chiou, Liang-Ying Lu, Zhao-Hong Chen, Yu-Hsiung Su, Jen-Chieh Yeh, Yi-Fan Chen and Shih-Che Lin, “System Thermal Analysis of 3D IC on ESL Virtual Platform,” IEEE International SoC Design Conference, pp.394-397, 2013
  18. Lih-Yih Chiou, Chi-Ray Huang, Chang-Chieh Cheng and Yu-Lin Tsai , “A 300mV Sub-1pJ Differential 6T Sub-threshold SRAM with Low Energy and Variability Resilient Local Assist Circuit,” in Proc. IEEE International Symposium on Next Generation Electronics, pp. 337-340, 2013.
  19. Lih-Yih Chiou, Liang-Ying Lu, Bo-Chi Lin and Alan P. Su, “Buffer Size Minimization Method Considering Mix-Clock Domains and Discontinuous Data Access,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 380-383, 2012.
  20. Shien-Chun Luo, Chi-Ray Huang and Lih-Yih Chiou, “Minimum Convertible Voltage Analysis for Ratioless and Robust Subthreshold Level Conversion,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 2553-2556, 2012
  21. Yi-Siou Chen, Lih-Yih Chiou, Hsun-Hsiang Chang, "A fast and effective dynamic trace-based method for analyzing architectural performance," ASP-DAC 2011: 591-596
  22. Lih-Yih Chiou, Yi-Siou Chen and Ya-Lun Jian, “Energy-Aware Partitioning for On-Chip Bus Architecture using a Multi-Objective Genetic Algorithm,” in the Int. Symp. on VLSI Design, Automation & Test (VLSI-DAT 2011).
  23. Shien-Chun Luo and Lih-Yih Chiou, "A subthreshold SRAM cell with autonomous bitline-voltage clamping," International Symposium on Next-Generation Electronics (ISNE), pp.150-153, 18-19 Nov. 2010. [EI]
  24. Lih-Yih Chiou, Yi-Siou Chen and Ya-Lun Jian, “Energy-Aware Partitioning Using a Multi-Objective Genetic Algorithm,” in Proc. Int. Workshop on Synthesis And System Integration of Mixed Information Techniques, Oct. 2010, pp. 407-411.
  25. Liang-Ying Lu, Tsung-Yi Wu, Lih-Yih Chiou, and Jing-Wen Shi, "Peak Current Reduction Using an MTCMOS Technique," 2nd Asia Symposium on Quality Electronic Design, pp. 255-259, Aug. 2010. [EI]
  26. Shien-Chun Luo and Lih-Yih Chiou,"Adaptive Minimum Supply Voltage for Subthreshold Circuits Considering Noise Margin and PT Variations", IEEE International Conference on Green Circuits and Systems (ICGCS), pp. 499-503, 2010. [EI]
  27. Lih-Yih Chiou, Hsin-Ei Lim, and Yi-Siou Chen, "Aggressive look-ahead earliest deadline first algorithm", IEEE Region 10 Conference, TENCON pp. 1-4, 2007. [EI]
  28. Lih-Yih Chiou and Shien-Chun Luo, "An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop", International Symposium on Circuit and System (ISCAS) 2007, pp. 1157-1160, 2007. [EI]
  29. P. Manikandan, B.D. Liu, L.Y. Chiou, G. Sundar, and C.R. Mandal, “Asynchronous Design Methodology for an Efficient Implementation of Low Power ALU,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2006), pp. 590-593, 2006.[Best Paper Award]
  30. Yen-Ting Liu, Lih-Yih Chiou, and Soon-Jyh Chang, "Energy-Efficient Adaptive Clocking Dual Edge Sense-Amplifier Flip-Flop," International Symposium on Circuit and System (ISCAS) 2006, pp. 4329-4332, 2006. [EI]
  31. C. H. Wu, Le-Ren Chang-Chien, Lih-Yih Chiou “Active Filter Based On-Chip Step-Down DC-DC Switching Voltage Regulator”IEEE Region 10 Conference / Tencon’05, November 2005, Melbourne, Australia. [EI]
  32. Lih-Yih Chiou, Hsieh-wei Lee, Sheau-Fang Lei, and Bin-Da Liu “Design and Implementation of an Efficient Architecture for Higher Order Statistics with DWT,”IEEE International symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT), pp.287-290, April 2005. [EI, IEEE]
  33. Heng-Yao Lin, Chi-Sheng Lin, Lih-Yih Chiou, Bin-Da Liu, "Leakage Current Reduction in CMOS Logic Circuits", IEEE Asia-Pacific Conference on Circuits and Systems, pp.349-352, 2004. [EI, IEEE]
  34. Meng-Fan Chang, Lih-Yih Chiou, Kuai-Ann Wen, “A LOW SUPPLY NOISE CONTENT-SENSITIVE ROM ARCHITECTURE FOR SOC,” IEEE Asia-Pacific Conference on Circuits and Systems, pp.1021-1024, May 2004. [EI, IEEE]
  35. Yongtao Wang, H. Madmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, and K. Roy, “Hardware Architecture and VLSI Implementation of a Low-Power High-Performance Polyphase Channelizer with Applications to Subband Adaptive Filtering,” IEEE International Conference on Acoustics, Speech, and Signal Processing, 2004 (ICASSP '04). , Vol. 5, pp.97 – 100, 2004. [EI, IEEE]
  36. Lih-Yih Chiou, Swarup Bhunia and Kaushik Roy, “Synthesis of Application-Specific Highly Efficient Multi-Mode Systems for Low-Power Applications,” Design, Automation and Test in Europe, pp.96-101, 2003. [IEEE]
  37. Lih-Yih Chiou, Khurram Muhammand and Kaushik Roy, “DSP Datapath Synthesis for Low-Power Applications,” IEEE International Conference on Acoustics, Speech, and Signal Processing, Vol. 2, pp. 1165-1168, May 2001. [EI, IEEE]
  38. L.Y. Chiou, K.M. Mahoney, K.T. Kornegay and A.M. Weiner, “Design of an Ultrafast Opti cal Processing Chip”, IEEE International Symposium on Circuits and Systems. v 4, IEEE, Piscataway, NJ, USA, pp. 109-112, 1996.
  39. Raghavi V. Cherabuddi, Lih-Yih Chiou and Magdy A. Bayoumi, “Simultaneous Parti tion, Scheduling and Allocation for Synthesis of Multiple-Chip Module Architecture,” IEEE Proceedings of the International Conference on the Economics of Design, Test, and Man ufacturing, pp.129-135, 1996. [EI]
  40. Lih-Yih Chiou, Jimmy Limqueco and M A. Bayoumi, “A VLSI architecture for modified frequency sensitive self-organizing neural network for image data compression,” Proceedings of IEEE Workshop on VLSI Signal Processing, pp. 418-424, 1994. [EI]
  41. Lih-Yih Chiou, Jimmy Limqueco, Jun Tian, C. Lursinsap and H. Chu, “Modified frequency sensitive self-organization neural network for image data compression,”World Congress on Neural Networks-San Diego. 1994 International Neural Network Society Annual Meeting. Lawrence Erlbaum Associates. Vol.1, 1994, pp. I/342-7.
Patent
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  1. Lih-Yih Chiou, Chi-Ray Huang, "Single port SRAM memory cell driven by two word lines in asynchronous manner and memory employing the same," U.S. Patent No. 9715922. (Issue dare: Jul. 25, 2017)
  2. 邱瀝毅、黃啟睿：「雙字線非同步驅動的記憶細胞及具此記憶細胞的記憶體」中華民國發明專利第I609375號。（公告日：2017/12/21）
  3. 邱瀝毅、簡才淦、李章嘉：「節能非揮發性微處理器」中華民國發明專利第 I522794號。（公告日: 2016/02/21）
  4. 邱瀝毅、黃啟睿、鄭昌杰：「具維持讀取訊號的隨機存取記憶體」中華民國發明專利第 I566246號。（公告日: 2017/01/11）
  5. 邱瀝毅、呂良盈：「積體電路熱模擬裝置及方法」中華民國發明專利第 I522830號。（公告日: 2016/02/21）
  6. Lih-Yih Chiou, Tsai-Kan Chien, "Non-volatile static random access memory," U.S. Patent 9734909. (Issue date: Aug. 15, 2017)
  7. 邱瀝毅、簡才淦、鄒亦淞：「一種非揮發性靜態隨機存取記憶體」中華民國發明專利第 I545564號。（公告日: 2016/08/11）
  8. Lih-Yih Chiou, Tsai-Kan Chien, "Content addressable memory and memory cell thereof," U.S. Patent 9646695. (Issue date: May. 9, 2017)
  9. 邱瀝毅、簡才淦：「一種記憶細胞及具該記憶細胞的內容可定址記憶體」中華民國發明專利第 I579860號。（公告日: 2017/04/21）
  10. Lih-Yih Chiou, Chi-Ray Huang, Kuan-Lin Wu, "Adaptive Data-Retention-Voltage Regulating System for SRAM," U.S. Patent 9123436. (Issue date: Sep. 1, 2015)
  11. 邱瀝毅、黃啟睿、吳冠麟：「靜態隨機存取記憶體之自適應性資料保持電壓調節系統」中華民國發明專利第 I498892號。（公告日: 2015/09/01）
  12. 邱瀝毅、黃啟睿、吳冠麟：「靜態隨機存取記憶體之自適應性資料保持電壓調節系統」中國大陸專利第CN104517638B號。（授權公告日: 2017/11/10）
  13. Lih-Yih Chiou, Chi-Ray Huang, Ming-Hung Wu, "In Situ Pulse-Based Delay Variation Monitor Predicting Timing Error Caused By Process and Environmental Variation," U.S. Patent 9094002. (Issue date: Jul. 28, 2015)
  14. 邱瀝毅、黃啟睿、吳旻鴻：「具有能預測因製程與環境變異所造成時序錯誤的嵌入式脈衝時序電路系統」中華民國發明專利第 I489245號。（公告日: 2015/06/21）
  15. 邱瀝毅、黃啟睿、吳旻鴻：「一種嵌入式脈衝時序電路系統」中國大陸專利第 CN103856192B號。（授權公告日: 2017/03/01）
  16. 邱宏達、邱瀝毅、徐銘佑、紀培偉：「步態分析裝置與應用其之跑步運動設備」中華民國發明專利第 I517875號。（公告日: 2016/01/21）
Others
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  1. 技術轉移技術名稱: 熱分析引擎技術; 授權單位: 國立成功大學; 接受單位: 工業技術研究院
Projects
  1. 國科會2004, 低功率特殊應用導向多模組式可重組化系統設計 (計劃主持人)
  2. 國科會2004, 嵌入式多媒體並行處理之低功率可重置式處理器矽核—子計畫三： 用於低功率多模組式介面電路設計 (1/3) (計劃主持人)
  3. 國科會2005, 嵌入式多媒體並行處理之低功率可重置式處理器矽核—子計畫三： 用於低功率多模組式介面電路設計 (2/3) (計劃主持人)
  4. 國科會2005, 可攜式低功率之視訊單晶片系統研發與應用—子計畫三：可攜式視訊單晶片中系統層面功率消耗探究平台之研究 (1/3) (計劃主持人)
  5. 國科會2006, 嵌入式多媒體並行處理之低功率可重置式處理器矽核—子計畫三： 用於低功率多模組式介面電路設計 (3/3) (計劃主持人)
  6. 國科會2006, 可攜式低功率之視訊單晶片系統研發與應用—子計畫三：可攜式視訊單晶片中系統層面功率消耗探究平台之研究 (2/3) (計劃主持人)
  7. 國科會2007, 可攜式低功率之視訊單晶片系統研發與應用—子計畫三：可攜式視訊單晶片中系統層面功率消耗探究平台之研究 (3/3) (計劃主持人)
  8. 國科會2007, 電子系統層級設計技術開發及其在多格式系統晶片之應用－子計畫五：電子系統層級功率評估與連接功率最佳化於多格式系統單晶片應用之研究(1/3)
  9. 國科會2008, 電子系統層級設計技術開發及其在多格式系統晶片之應用－子計畫五：電子系統層級功率評估與連接功率最佳化於多格式系統單晶片應用之研究(2/3)
  10. 國科會2009, 電子系統層級設計技術開發及其在多格式系統晶片之應用－子計畫五：電子系統層級功率評估與連接功率最佳化於多格式系統單晶片應用之研究(3/3)
  11. 國科會2010, 具易除錯特性之智慧型低功率多核心系統之設計技術研發：從電子系統層級至矽晶片層級－子計畫三：具除錯特性且考慮功率和熱管理之智慧型傳輸架構探勘(1/3)
  12. 國科會2011, 具易除錯特性之智慧型低功率多核心系統之設計技術研發：從電子系統層級至矽晶片層級－子計畫三：具除錯特性且考慮功率和熱管理之智慧型傳輸架構探勘(2/3)
  13. 國科會2012, 具易除錯特性之智慧型低功率多核心系統之設計技術研發：從電子系統層級至矽晶片層級－子計畫三：具除錯特性且考慮功率和熱管理之智慧型傳輸架構探勘(3/3)
  14. 國科會2013,考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法－子計畫一：適用於高能源效益三維晶片之智慧型功率與溫度管理架構及電路之研發(1/3)
  15. 國科會2014,考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法－子計畫一：適用於高能源效益三維晶片之智慧型功率與溫度管理架構及電路之研發(2/3)
  16. 國科會2015,考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法－子計畫一：適用於高能源效益三維晶片之智慧型功率與溫度管理架構及電路之研發(3/3)
  17. 國科會2015, 具能量效率之異質性架構系統中介語言GPU之設計與實現－子計畫三：應用於HSAIL GPU之具能耗效率系統架構設計探勘及實現
  18. 科技部2016, 具能量效率之OpenCL及OpenGL HSA相容GPU系統設計與實作 (共同主持人)
  19. 科技部2018, 符合OpenCL/TensorFlow API 規範的終端AI 處理器(1/4)
  20. 科技部2018, 具高安全性且低耗能之物聯網晶片電路及系統之分析、設計與實作-子計畫一：具硬體安全性及能量效益的物聯網微處理器及記憶體設計之研究(1/2) (計畫主持人)
  21. 科技部2019, 符合OpenCL/TensorFlow API 規範的終端AI 處理器(2/4) （共同主持人）
  22. 科技部2019, 具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作－總計畫暨子計畫六：數位電路設計及測試架構之安全性分析及防駭技術(2/2) （共同主持人）
  23. 科技部2019, 具高安全性且低耗能之物聯網晶片電路及系統之分析、設計與實作-子計畫一：具硬體安全性及能量效益的物聯網微處理器及記憶體設計之研究(2/2) （計畫主持人）
  24. 科技部2020, 符合OpenCL/TensorFlow API 規範的終端AI 處理器(3/4) （共同主持人）
  25. 科技部2020, 具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作－總計畫暨子計畫六：數位電路設計及測試架構之安全性分析及防駭技術(1/2) （共同主持人）
  26. 科技部2020, 具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-子計畫一：具硬體安全性及能量效益的物聯網微處理器及記憶體設計之研究(1/2) （計畫主持人）
  27. 科技部2021, 符合OpenCL/TensorFlow API 規範的終端AI 處理器(4/4) （共同主持人）
  28. 科技部2021, 具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作－總計畫暨子計畫六：數位電路設計及測試架構之安全性分析及防駭技術(2/2) （共同主持人）
  29. 科技部2021, 具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-子計畫一：具硬體安全性及能量效益的物聯網微處理器及記憶體設計之研究(2/2) （計畫主持人）
Classes
2015Fall
2015Spring
2016Fall
2016Spring
2017Fall
2017Spring
2018Fall
2018Spring
2019Spring
2020Fall
2020Spring
2021Fall
2022 Spring
Students
Current Academic Year Lab Members
Master
潘姵羽
張辰維
許舜修
陳柏瑄
楊俊文
洪毅玄
蘇柏銜
彭文彥
葉孟韋
邱崇傑
陳奕廷
陳志瑜
潘鴻福
Vijay Maddi
劉永勝
蔡宗瑾
謝懷頡
陳志芳
陳俊安
呂維霆
白承宏
林靖洋
Graduates of all Previous Years
Master
94
黃瑞祥   楊秉勳
95
許哲懋   高秉佑   劉書宏   林信義   王育建
96
郭子齊   黃建霖   邱詠偉   蘇家緯   吳俊賢
97
簡亞倫   李致賢   陳顗合   胡燈嬛   吳立璿   林惠禎   吳炫德
98
周玉珊   黃啟睿   張巽翔   洪佳琪
99
歐承政   林伯齊   吳旻鴻
100
馮業駿   蕭育書   翁培恩   吳冠麟   柯柏州
101
蔡侑霖   陳昭宏   李宗儒
102
蘇鈺雄   林暐哲   鄒亦淞   鄭昌杰
103
謝宗諭   林玠佑   林璟謙   莊曜駿   李章嘉
104
劉政威   柯盛瀚   鄭傑文   張啟賢
105
黃境昱   羅聖凱   楊朝凱   賴祈叡   胡士皇
106
楊維軒   楊宗翰   楊品修   吳忠翰   張易溥
107
魏柏丞   張哲彬   張晉維   江俊興   徐健棠
108
張峻豪   謝憲譁   李紀寬   林育緯   杜唯宏    黃俊修   游凱名   蘇美佳   黃尹鐶
109
李昱宏   蔡宗蕙   凌偉碩   林志展   林聖凱   陳錫峰   蘇巴坦
110
張琬筠   陳韻如
111
曾心妤   鄭中凱   林晨哲   蔡鎮中   楊子毅   施泓名   呂芝儀   陳宗琪   李宗翰   鄧士瑩   賴昶融   楊竣文   鄭俊升
Ph.D.
100
陳怡秀   羅賢君
106
呂良盈   簡才淦
109
黃啟睿   黃啟睿
Honors
  1. (2021)指導大學部學生許舜修、楊竣文– 獲得教育部109學年度大學校院積體電路設計競賽--標準元件數位電路設計組佳作
  2. (2020)指導大學部學生施泓名、呂芝儀– 獲得教育部108學年度大學校院積體電路設計競賽--標準元件數位電路設計組佳作
  3. (2020)第二十屆旺宏金矽獎-設計組評審團銅獎
  4. (2019)未來科技突破獎, MOST科技部
  5. (2018) Execuitive Secretary, VLSI Desogn/CAD Symposium
  6. (2018) 指導大學部學生張琬筠、侯雅勻– 獲得教育部106學年度大學校院積體電路設計競賽--標準元件數位電路設計組優等
  7. (2018-2019) Member of BoG, IEEE Tainan Section
  8. (2018) General Co-Chair, International Symposium on VLSI-DAT
  9. (2017) Program Chair, International Symposium on VLSI-DAT
  10. (2017) 優良導師，國立成功大學電資學院
  11. (2016-2017) Treasurer, IEEE Tainan Section
  12. (2016) General Co-Chair, Taiwan and Japan Conference on Circuits and Systems
  13. (2016) Tutorial Chair, International Symposium on VLSI-DAT
  14. (2015-2016) Chairman, IEEE Tainan CASS Chapter
  15. (2016) 指導碩士班 研究生吳忠翰、魏柏丞 – 獲得教育部104學年度大學校院積體電路設計競賽--全客戶電路設計組佳作
  16. (2015) 指導碩士班 研究生張易溥、楊品修 – 獲得教育部104學年度大學校院積體電路設計競賽--標準元件數位電路設計組特優
  17. (2014) 國立成功大學教學特優教師
  18. (2013) 102年度國科會整合型計劃「績優計畫獎」，計畫主持人：李昆忠教授(總主持人)、陳中和教授、邱瀝毅教授、張順志教授、蔡建泓教授、郭致宏教授、蘇文鈺教授、林家民教授。
  19. (2013) 指導碩士班 研究生李章嘉、林璟謙 – 獲得教育部101學年度大學校院積體電路設計競賽--數位IC組優等
  20. (2012-2016) 共同主持人，智慧電子整合性人才培育先導型計畫-綠能電子聯盟
  21. (2011) 執行秘書，智慧電子整合性人才培育先導型計畫-綠能電子聯盟
  22. (2011) 國立成功大學教學優良教師
  23. (2011) 指導碩士班 研究生黃啟睿、蔡侑霖 – 獲得教育部 99 學年度大學校院積體電路設計競賽--全客戶式設計組佳作
  24. (2010) 指導碩士班 研究生馮業駿、蕭育書 – 獲得教育部 98 學年度大學校院積體電路設計競賽--數位IC組優等
  25. (2008-2009) 課程開發主持人，前瞻晶片系統設計人才培育先導型計畫-異質整合系統設計
  26. (2006-2007) 執行秘書，前瞻晶片系統設計人才培育先導行計畫-系統層級設計(SLD)聯盟
  27. (2006) 最佳論文獎，IEEE Asia Pacific Conference on Circuits and Systems(APCCAS)
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