NCKUEE Faculty Data
Chinese Version
Associate Professor Yean-Ru Chen
Address
ChiMei Building 6F R95607
Email
TEL
+886-6-2757575 ext.62321
Lab Weblink
Computer-Aided Verification Lab
(R95614/ext.62400-2817)
Background
Educations
2014
Ph.D., Graduate Institute of Electronics Engineering, National Taiwan University
2006
M.S., Department of Computer Science and Information Engineering, National Chung Cheng University
2002
B.S., Department of Computer Science and Information Engineering, National Chiao Tung University
Experiences
2016/08-present
Assistant Professor, Department of Electrical Engineering, National Cheng Kung University
2015/05-2016/07
Lead Application Engineer, Cadence Design Systems, Inc.
2014/05-2015/01
Senior Engineer, MediaTek Inc.
2002/07-2003/09
Assistant Engineer, Industrial Technology Research Institute
Specialities
  • Formal methods, including model checking, theorem proving and etc.
  • Functional safety verification methodology development
  • Data/On-chip security verification
  • Digital circuit design
  • Artificial neural network application on verification research
  • Quantum circuit design and verification
Publication
Journal
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  1. Chen, Y. R., Hsu, C. H., Li, T. F., Lin, C. Y., Weng, S. C. & Tsai, M. Y., “Automatic Model Transformation and Formal Verification for Function Block of IEC 61499,” Software and Systems Modeling, Accepted/In press, 2025.
  2. Wang, Y. T., Lin, T. Y., Sou, S. I., Chen, L. A., Tsai, M. H., Chen, Y. R. & Tu, C. H., “Markov Clustering-Based Content Placement in Roadside-Unit Caching With Deadline Constraint,” IEEE Transactions on Intelligent Transportation Systems, 25(9), pp. 11881-11892, 2024.
  3. Chen, Y. R., Chiu, C. C. & Chen, H., “Robustness Analysis of Neural Network Designs with Sparsity Investigation,” Journal of Information Science and Engineering, 40(3), pp. 595-614, May 2024.
  4. Chen, Y. R., Wang, T. F., Chen, S. H. & Kao, Y. C., “Empirical study on security verification and assessment of neural network accelerator,” Microprocessors and Microsystems, Vol. 99, June 2023, 104845.
  5. Chen, Y. R., Chen, S. H. & Lin, S. W., “SMT Solver With Hardware Acceleration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 42(6), pp. 2055-2068, June 2023.
  6. Lin, T. Y., Wang, C. Y., Tuan, Y. P., Tsai, M. H. & Chen, Y. R., “A Study on Traffic Asymmetry for Detecting DDoS Attack in P4-based SDN,” Journal of Information Science and Engineering, 38(6), pp. 1265-1283, Nov. 2022.
  7. Y.-R. Chen, J.-J. Yeh, P.-A. Hsiung, and S.-J. Chen, “Accelerating Coverage Estimation through Partial Model Checking,” IEEE Transactions on Computers, Computer 63(7): pp. 1613-1625, 2014.
  8. C.-S. Lin, P.-A. Hsiung, S.-W. Lin, Y.-R. Chen, C.-H. Lu, S.-Y. Tong, W.-T. Su, W. C. Chu, C.-H. Shih, N.-L. Hsueh, C.-H. Chang, and C.-S. Koong, "VERTAF/Multi-Core: A SysML-based Application Framework for Multi-Core Embedded Software Development," Journal of the Chinese Institute of Engineers, Vol. 32, No. 7, pp. 985-991, November 2009 (SCI).
  9. P.-A.Hsiung, S.-W.Lin, Y.-R.Chen, C.-H.Huang, and W. C. Chu, "Modeling and Verification of Real-Time Embedded Systems with Urgency," Journal of Systems and Software (JSS) (SCI), Volume 82, No. 10, pp. 1627-1641, Elsevier Inc., October 2009.
  10. P.-A. Hsiung, Y.-R. Chen and Y.-H. Lin, "Model Checking Safety-Critical Systems using Safecharts," IEEE Transactions on Computers (SCI), Vol. 56, No. 5, pp. 692-705, May 2007.
  11. Y.-R. Chen and P.-A. Hsiung, "Automatic Failure Analysis using Safecharts," International Journal of Software Engineering and Knowledge Engineering (IJSEKE) (SCI), Vol. 17, No. 1, pp. 57-78, World Scientific Publishing, Singapore, February 2007.
Conference
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  1. Ting, C. C., Huang, Y. T., Chen, Y. T., Chen, Y. R. & Lin, E. H., “Spectre Attack Detection with Formal Method on RISC-V Processor at RTL Design Level,” VLSI TSA 2025 - Proceedings of Technical Papers, IEEE, 2025.
  2. Lin, C. C., Yan, J. Q. & Chen, Y. R., “Stabilizer-Based Dynamic Assertion Circuits (SBDACs) for Quantum Circuits,” VLSI TSA 2025 - Proceedings of Technical Papers, IEEE, 2025.
  3. Lin, S. W., Wang, T. F., Chen, Y. R., Hou, Z., Sanán, D. & Teo, Y. S., “A Parallel and Distributed Quantum SAT Solver Based on Entanglement and Teleportation,” TACAS 2024, ETAPS 2024, Proceedings, LNCS 14571, Springer, pp. 363-382, 2024.
  4. Lin, C. N., Lin, S. W. & Chen, Y. R., “Dynamic Assertions for Quantum Circuits Based on Stabilizers,” Quantum Technologies 2022, SPIE Proceedings, Vol. 121330, 2022.
  5. Lin, C. H., Su, Y. P., Chen, Y. R., Chou, Y. T. & Chen, S. J., “Empirical Study of Proposed Meltdown Attack Implementation on BOOM v3,” MWSCAS 2022 - 65th IEEE International Midwest Symposium on Circuits and Systems, Proceedings, 2022.
  6. Chen, H., Su, Y. P., Chen, Y. R., Chiu, C. C. & Chen, S. J., “Robustness Analysis of Neural Network Designs for ReLU Family and Batch Normalization,” IC TAAI 2022 - Proceedings of 2022 International Conference on Technologies and Applications of Artificial Intelligence, IEEE, pp. 1-6, 2022.
  7. Ke, C. S. & Chen, Y. R., “Instruction Verification of Ethereum Virtual Machine by Formal Method,” Indo-Taiwan ICAN 2020 - Proceedings, IEEE, pp. 69-74, Feb. 2020.
  8. Y.-R. Chen, S.-J. Chen, P.-A. Hsiung, I-H. Chou, “Unified Security and Safety Risk Assessment - A Case Study on Nuclear Power Plant,” TSA 2014: 22-28
  9. Y.-R. Chen, Z.-R. Wong, P.-A. Hsiung, S.-J. Chen and M.-H. Tsai, “Backward Probing Deadlock Detection for Networks-on-chip,” International Symposium on Networks-on-Chip (NOCS), April 2013.
  10. H.-L. Chao, Y.-R. Chen, S.-Y. Tong, P.-A. Hsiung, S.-J. Chen, “Congestion-aware scheduling for NoC-based reconfigurable systems,” Design, Automation & Test in Europe Conference & Exhibition (DATE), March 2012.
  11. Y.-R. Chen , W.-T. Su, P.-A. Hsiung, Y.-C. Lan, Y.-H. Hu, and S.-J. Chen, "Formal Modeling and Verification of Network-on-Chip," Proceedings of the International Conference on Green Circuits and Systems, 2010.
  12. Y.-R. Chen, T.-Y. Chen, P.-A. Hsiung, S.-J. Chen and Y.-H. Hu, "Compositional Automata Reduction with Non-critical Path Slicing," The 2009 International Conference on Foundations of Computer Science, pp. 133-138, CSREA Press, July 2009.
  13. P.-A. Hsiung, C.-S. Lin, S.-W. Lin, Y.-R. Chen, C.-H. Lu, S.-Y. Tong, W.-T. Su, C. Shih, C.-S. Koong, N.-L. Hsueh, C.-H. Chang, William C. Chu, "VERTAF/Multi-Core: A SysML- based Application Framework for Multi-Core Embedded Software Development," Proceedings of the International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), LNCS, Springer Verlag, June 2009.
  14. P.-A. Hsiung, S.-W. Lin, Y.-R. Chen, N.-L. Hsueh, C.-H. Chang, C.-H. Shih, C.-S. Koong, C.-S. Lin, C.-H. Lu, S.-Y. Tong, W.-T. Su, and W. C. Chu, "Model-Driven Development of Multi-Core Embedded Software," Proceedings of the 2nd International Workshop on Multicore Software Engineering (IWMSE), May 2009.
  15. Y.-R. Chen, P.-A. Hsiung, and S.-J. Chen, "Modeling and Automatic Failure Analysis of Safety-Critical Systems using Extended Safecharts," Proceedings of the International Conference on Computer Safety, Reliability and Security (SAFECOMP, Nuremberg, Germany), Lecture Notes in Computer Science (LNCS), Springer Verlag, September 2007.
  16. P.-A. Hsiung , S.-W. Lin, Y.-R. Chen, C.-H. Huang, J.-J. Yeh, H.-Y. Sun, C.-S. Lin, and H.-W. Liao, "Model Checking Timed Systems with Urgencies," Proceedings of the 4th International Symposium on Automated Technology for Verification and Analysis (ATVA, Beijing, China), LNCS Vol. 4218, pp. 67-81, Springer-Verlag, October 2006.
  17. S.-W. Lin, P.-A. Hsiung , C.-H. Huang, and Y.-R. Chen, "Model Checking Prioritized Timed Automata," Proceedings of the 3rd International Symposium on Automated Technology for Verification and Analysis (ATVA, Taipei, Taiwan), LNCS Vol. 3707, pp. 370-384, Springer Verlag, October 2005.
Patent
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Others
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  1. Ebook Editor: P.-A. Hsiung , Y.-H. Lin, and Y.-R. Chen, "Safecharts Model Checking for the Verification of Safety-Critical Systems," in Verification, Validation and Testing in Software Engineering , editors Aristides Dasso, Ana Funes, IDEA Group, Inc., USA, ISBN: 1-59140-851-2, 2007.
  2. Invited Reviewer of IEEE Transactions on Computers
  3. Invited Reviewer of International Symposium on Automated Technology for Verification and Analysis
Projects
  1. Principal Investigator: Formal Verification (RealTek, Inc.) , 2018/03 -
  2. Principal Investigator: Development of a Scalable Formal Verification, Failure and Causality Analysis Tool Set for Safety-Critical Internet-of-Things Systems (MOST 106 - 2218 - E - 006 - 012), 2017/03 - 2018/02
  3. Project Executor: Research on Information Security and Asset Management in Nuclear Power Plants (Project code: 1002001INER001), 2011/01-2011/12
  4. Project Executor: National Science Council sponsored International Collaboration Research Project (NSC 97-2221-E002-241-MY3),Research on the Development of a Hierarchical Network-on-Chip System Platform Synthesizer, 2008-2011
  5. Project Executor: National Taiwan University and SpringSoft (Synopsys) Inc. , Electronic System Level (ESL) Design Project, 2007-2008
Classes
2024 Spring
2024 Fall
2023 Spring
2023 Fall
2022 Spring
2022 Fall
2021 Spring
2021 Fall
2020 Spring
2020 Fall
2019 Spring
2019 Fall
2018 Spring
2018 Fall
2017 Spring
2017 Fall
Students
Current Academic Year Lab Members
Master
Min-Yan Tsai
Zhao-Jun Deng
Yi-Ting Lee
Yu-Shien Shen
Chi-Lun Lu
Tian-Fu Lee
Jing-Wei Wang
Ji-Qing Yan
Chia-Wei Chang
Li-Jun Hsu
Li-Jung Chen
Yu-Tong Chen
Nian-Hong Wu
Shun-Yu Li
Cheng-Kai Sie
Yu-Ming Lai
Jing-Yao Jhong
Kun-Wei Yen
Po-Sheng Chen
Bo-Han Hong
Graduates of all Previous Years
Master
106
Ming-Lin Lu   Yen-Ting Liu
107
Jin-Wei Lian   Shi-Wei Wu   Zhwn-Ting Gao   Yi-Jyun Gao
108
Jia-Hao Syu   Tien-Yin Chang   Chun-Sheng Ke
110
Lee-Ming Tan   Sheng-Lung Huang   Chia-Hsien Yang   Hang Chen   Chih-Cheng Ting   Yu-Ting Huang   Shi-Han Chen   Chi-Kai Wang
111
Yu-Ting Chou   Shao-Chia Weng   Chien-Hsiang Lin   Cheng-Yuan Lin
112
Chao-Yu Wang   Kuan-Ming Lin   Chi-Chieh Chiu   Sheng-Ran Wei   Tzu-Chieh Yen   Tzu-Fan Wang
Honors
  1. Visiting Scholar, the University of Wisconsin-Madison, Madison Madison, WI, USA, Department of Electrical and Computer Engineering, 2009.
  2. Annual Excellent Thesis Award of Institute of Information & Computing Machinery, 2006.
NCKU EE