Faculty Data - NCKUEE

Professor Kuo-Hsing Kao

Address

ChiMei Building 4F R95402

TEL

+886-6-2757575 ext.62419

Lab Weblink

KLAB

(R95A06/ext.62400-2206)

Background

Educations

2013

PhD, Electrical Engineering, KULeuven, Belgium

2008

MS, Electrophysics, National Chiao Tung University, Taiwan

2005

BS, Physics, National Chung Hsing University, Taiwan

Experiences

2014~now

Faculty Member, Department of Electrical Engineering, National Cheng Kung University, Taiwan

2024~now

tsmc assignee in EU

2019~2024

Visiting Scholar, imec/KULeuven, Belgium

2009-2013

PhD researcher, Inter-university Microelectronic Centre (imec), Belgium

Specialities

Semiconductor Physics and Devices

Publication

Journal

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“Study of endurance performance of SiO2 interfacial layer scaling through O scavenging in Si Channel n-FeFET with Si:HfO2 ferroelectric layer”, IEEE Trans. Electron Devices, accepted, 2024.
“Device Simulations with A U-Net Model Predicting Physical Quantities in Two-Dimensional Landscapes”, Sci. Rep., 13, 731, 2023.
“First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications”, IEEE Trans. Electron Devices, 69, 2101, 2022.
“Linking Room- and Low-Temperature Electrical Performance of MOS Gate Stacks for Cryogenic Applications”, IEEE Electron Device Lett., 43, 674, 2022.
“First demonstration of ferroelectric tunnel thin-film transistor non-volatile memory with polycrystalline-silicon channel and HfZrOx gate dielectric”, IEEE Trans. Electron Devices, 69, 11, 6072, 2022.
“Inherent Dipole Layer Formation Driven by Surface Energy at Nonplanar Dielectric Interfaces”, IEEE Trans. Electron Devices, 68, 294, 2021.
"Subthreshold Swing Saturation of Nanoscale MOSFETs Due to Source-to-Drain Tunneling at Cryogenic Temperatures”, IEEE Electron Device Lett., 41, 1296, 2020.
“Fabrication of Vertically Stacked Nanosheet Junctionless Filed-Effect Transistors and Applications for the CMOS and CFET Inverters”, IEEE Trans. Electron Devices, 67, 3504, 2020.
“Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs”, IEEE Trans. Electron Devices, 66, 2509, 2019.
“Significance of Multivalley and Nonparabolic Band Structure for GeSn TFET Simulation”, IEEE Trans. Electron Devices, 65, 4709, 2018.
“Junctionless FETs with a Fin Body for Multi-VTH and Dynamic Threshold Operation”, IEEE Trans. Electron Devices, 65, 3535, 2018.
“A FET with a Source Tunneling Barrier Showing Suppressed Short Channel Effects for Low Power Applications”, IEEE Trans. Electron Devices, 65, 855, 2018.
“Improving the Electrical Performance of a Shell Doping Profile Quantum Well Transistor by Heterojunction Optimization”, IEEE Trans. Electron Devices, 64, 3563, 2017.
“Undoped and Doped Junctionless FETs: Source/Drain Contacts and Immunity to Random Dopant Fluctuation”, IEEE Electron Device Lett., 38, 708, 2017.
“A Dopingless FET with Metal-Insulator-Semiconductor Contacts”, IEEE Electron Device Lett., 38, 5, 2017.

Conference

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“Insight into Latchup Risk in 28nm Planar Bulk Technology for Quantum Computing Applications”, IEEE IRPS, 8C.1, 2024.
“First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure”, IEEE IEDM Tech. Dig., 2-6, 2023.
“MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization”, IEEE ESSDERC, 9, 2023.
“How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology”, VLSI Tech. Dig., T13-3, 2023.
“First Demonstration of Heterogeneous L-shaped Field Effect Transistor (LFET) for Angstrom Technology Nodes”, IEEE IEDM Tech. Dig., 20.2.1, 2022.
“Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size”, IEEE IEDM Tech. Dig., 20.5.1, 2022.
“First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering”, VLSI Tech. Dig., 399, 2022.
“First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications”, IEEE IEDM Tech. Dig., 34.4.1, 2021.
“3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers”, IEEE IEDM Tech. Dig., 12.2.1, 2020.
“First Demonstration of Heterogeneous Complementary FETs Utilizing Low-Temperature (200 oC) Hetero-Layers Bonding Technique (LT-HBT)”, IEEE IEDM Tech. Dig., 15.5.1, 2020.
“Process and Structure Considerations for the Post FinFET Era”, IEEE SNW, 3.1, 13, 2020.

Patent

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Line-tunneling tunnel field-effect transistor (tfet) and manufacturing method. United States patent, No. 7460550, Dec. 2008
A. S. Verhulst and K.-H. Kao, 2012, "Line-tunneling tunnel field-effect transistor (tfet) and manufacturing method" USA Patent No. 20120298959 A1

Others

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Projects

(2024-2028) Extending Silicon Era by Superconductivity, Lighting and Anisotropy for Quantum Technology (under review).
(2023-2025) Si Superconductivity Experimental Demonstration and Ab Initio Calculation.
(2022-2023) Core Cryogenic Devices for High-Performance Computing and Quantum Computing.
(2018-2023) Futuristic Quantum Electronics and Artificial Intelligent Applications for Semiconductor Industry: Machine-Learning-Based Quantum Transport Modeling and CMOS-Compatible Device Fabrication.
(2017-2019) Dopantless FETs: NEGF Simulation and Experiment.
(2016-2017) Depletion Mode Quantum Well FETs: Simulation and Experiment.
(2015-2016) Quantum Electronic Devices with Shell Doping Profiles (Depth < 5 nm and Steepness ~ 0.7 nm/dec) for Energy-Efficient Applications.
(2014-2015) Modeling and Simulation of Strained GeSn Tunnel Field Effect Transistors.

Classes

2015 Spring