Tsung-Han Tsou, Dun-Jie Chen, Sheng-Yang Hung, Yu-Hsiang Wang, Chung-Ho Chen, Optimization of Stride Prefetching Mechanism and Dependent Warp Scheduling on GPGPU, 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Oct 12-14, 2020, Seville, Spain
Min Zhi Ji, Wei Chung Tseng, Ting Jia Wu, Bo Rong Lin, Chung Ho Chen, Micro Darknet for Inference: ESL reference for inference accelerator design, 16th International System-on-Chip Design Conference, ISOCC 2019, Oct 06-09, 2019,Jeju, Korea
Yu Xiang Su, Jhi Han Jheng, Dun Jie Chen, Chung Ho Chen, Development of an Open ISA GPGPU for Edge Device Machine Learning Applications, 11th International Conference on Ubiquitous and Future Networks, ICUFN 2019, July 02-05, 2019, Zagreb, Croatia
Sen Chih Tsai, Yu Xiang Su, Yu Han Chin, Wei Zhong Ceng, Chung Ho Chen,Kernel Aware Warp Scheduler, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, May 27-30, 2018, Italy
J.-W. Lin , and Chung-Ho Chen,Processor Shield for L1 Data Cache Software-Based On-line Self-testing, in Asia South Pacific Des. Autom. Conf. , January 16-19, 2017, Japan
J.-W. Lin , and Chung-Ho Chen,A Processor Shield for Software-Based On-Line Self-Test, in IEEE Asia Pacific Conf. Circuits and Systems, October 25-28, 2016, Korea
Yun-Chi Huang, Kuan-Chieh Hsu, Wan-shan Hsieh, Chen-Chieh Wang, Chia-Han Lu, and Chung-Ho Chen_,Dynamic SIMD Re-convergence with Paired-Path Comparison , in the 2016 IEEE International Symposium on Circuits and Systems (ISCAS), May 23-25, 2016, Montreal, Canada.
Yung Hsu and Chung-Ho Chen, A Heterogeneous System Architecture Conformed GPU Platform Supporting OpenCL and OpenGL, Taiwan and Japan Conference on Circuits and Systems (TJCAS), Aug. 18-23, 2015, Japan
Heng-Yi Chen, and Chung-Ho Chen, An HSAIL ISA Conformed GPU Platform, In International Conference on Innovation, Communication and Engineering (ICICE), Oct 23-28. 2015. Xiangtan, Hunan, P.R. China
Chien-Hsuan Yen, Kuan-Chung Chen and Chung-Ho Chen, A memory-efficient NoC system for Op0enCL many-core platform, in the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 24-27, 2015, Lisbon, Portugal.
Ching-Wen Lin and Chung-Ho Chen, Unambiguous I-cache testing using software-based self-testing methodology, in the 2014 IEEE International Symposium on Circuits and Systems (ISCAS), June 1-5, 2014 ,Melbourne VIC, Australian.
Kuan-Chung Chen and Chung-Ho Chen, An OpenCL Runtime System for a Heterogeneous many-Core Virtual Platform , in the 2014 IEEE International Symposium on Circuits and Systems (ISCAS), June 1-5, 2014 ,Melbourne VIC, Australian.
Jhe-Yu Liou and Chung-Ho Chen, Re-visit Blocking Texture Cache Design for Modern GPU, in the 11th International SoC Design Conference (ISOCC), Nov. 3-6, 2014, Jeju, Korea.
Tzu-Hsuan Hsu, Ching-Wen Lin and Chung-Ho Chen, Using Condition Flag Prediction to Improve the Performance of Out-of-Order Processors, in the IEEE International Symposium on Circuits and Systems (ISCAS), May 19-23, 2013 ,Beijing, China.
Chien-Te Liu, Kuan-Chung Chen and Chung-Ho Chen, CASL Hypervisor and its Virtualization Platform, in the IEEE International Symposium on Circuits and Systems (ISCAS), May 19-23, 2013 ,Beijing, China.
Hsu-Yao Huang, Chi-Yuan Huang, and Chung-Ho Chen,Tile-Based GPU Optimizations through ESL Full System Simulation,in the IEEE International Symposium on Circuits and Systems (ISCAS),May 20-23, 2012, Seoul, Korea.
Chen-Chieh Wang, Sheng-Hsin Lo, Yao-Ning Liu, and Chung-Ho Chen,NetVP: A System-Level NETwork Virtual Platform for Network Accelerator Development,in the IEEE International Symposium on Circuits and Systems (ISCAS),May 20-23, 2012, Seoul, Korea.
Chen-Chieh Wang and Chung-Ho Chen,An Optimized Cryptographic Processing Unit for IPsec Processors,in the 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC),June 19-22, 2011, Gyeongju, Korea.
Kuan-Chung Chen and Chung-Ho Chen,A Synchronization Profiler for Hybrid Full System Simulation Platform,in the International SoC Design Conference (ISOCC-2010),Nov. 22-23, 2010, Incheon, Korea.
Xie-Zeng Shen, Shin-Ying Lee, and Chung-Ho Chen,Full System Simulation with QEMU: an Approach to Multi-View 3D GPU Design,in the IEEE International Symposium on Circuits and Systems (ISCAS) ,May 30 - June 2, 2010, Paris, France.
Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen , and Kuen-Jong Lee,Full System Simulation and Verification Framework,in the Proceedings of the Fifth International Conference on Information Assurance and Security (IAS-2009) ,August 18-20, 2009, Xi'an, China.
Chen-Chieh Wang, Ro-Pun Wong, Jing-Wun Lin, and Chung-Ho Chen,System-Level Development and Verification Framework for High-Performance System Accelerator,in the IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT) ,April 27-30, 2009, Hsinchu, Taiwan.
Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, Chung-Ho Chen,A Software-Based Test Methodology for Direct-Mapped Data Cache,in the IEEE Seventeenth Asian Test Symposium (ATS) ,November 24-27, 2008, Sapporo, Japan.
Wei-Cheng Lin and Chung-Ho Chen,Avoiding Unnecessary Frame Memory Access and Multi-Frame Motion Estimation Computation in H.264/AVC,in the IEEE International Symposium on Circuits and Systems (ISCAS),May 18-21, 2008, Seattle, Washington, USA.
Tai-Hua Lu, Chung-Ho Chen , and Kuen-Jong Lee,A Hybrid Self-Testing methodology of Processor Cores,in the IEEE International Symposium on Circuits and Systems (ISCAS),May 18-21, 2008, Seattle, Washington, USA.
Yi-Ying Tsai, Chia-Jung Hsu, and Chung-Ho Chen ,Address Compression for Scalable Load/Store Queue Implementation,in the IEEE International Symposium on Circuits and Systems (ISCAS),May 18-21, 2008, Seattle, Washington, USA.
Tai-Hua Lu, Chung-Ho Chen, and Kuen-Jong Lee,A Hybrid Software-Based Self-Testing methodology for Embedded Processor,in the ACM Symposium on Applied Computing (SAC),March 16-20, 2008, Fortaleza, Ceara, Brazil. (EI)
Yi-Ying Tsai, Chia-Jung Hsu, and Chung-Ho Chen,Power-efficient and Scalable Load/Store Queue Design via Address Compression,in the ACM Symposium on Applied Computing (SAC),March 16-20, 2008, Fortaleza, Ceara, Brazil. (EI)
Wei-Cheng Lin and Chung-Ho Chen,A Data-Reuse Scheme for Avoiding Unnecessary Frame Buffer Accesses and Display RAM Accesses in MPEG-4 ASP Video Decoder,in the IEEE International SoC Conference (SOCC),September 26-29, 2007, Hsinchu, Taiwan.
Yi-Cheng Chung, Stanley Lee, and Chung-Ho Chen,A Packet Forwarding Method for the iSCSI Virtualization Switch,in the 4th International Workshop on Storage Network Architecture and Parallel I/Os (SNAPI),September 24, 2007, San Diego, California, USA.
Wei-Cheng Lin and Chung-Ho Chen,Reduction of Frame Memory Accesses and Motion Estimation Computations in MPEG-4 Video Encoder,in the 16th International Conference on Computer Communications and Networks (ICCCN),August 13-16, 2007, Honolulu, Hawaii, USA.
Chung-Ho Chen, Yi-Cheng Chung, Chen-Hua Wang, and Han-Chiang Chen,Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator,in the 31st Annual IEEE Conference on Local Computer Networks (LCN),November 14-16, 2006, Tampa, Florida, USA.
Kuo-Su Hsiao and Chung-Ho Chen,Scheduler Optimization by Exploring Wakeup Locality,in the International Conference of Computer Engineering & Systems (ICCES),November 5-7, 2006, Egypt.
Chung-Ming Chen, Chung-Ho Chen, Jian-Ping Zeng, and Chao-Tang Yu,Windows Processing for Deblocking Filter in H.264/AVC,in the Proceeding of the 32nd Annual Conference of the IEEE Industrial Electronics (IECON),November 7-10, 2006, Paris, France.
Kuo-Su Hsiao and Chung-Ho Chen,Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling,in the International Conference of Computer Design,October, 2006, USA. (EI)
Wei-Cheng Lin and Chung-Ho Chen,Exploring Reusable Frame Buffer Data for MPEG-4 Video Decoding,in the IEEE International Symposium on Circuits and Systems (ISCAS),2006, Island of Kos, Greece. (EI)
Chung-Ming Chen, Jian-Ping Zeng, Chung-Ho Chen, Chao-Tang Yu, and Yu-Pin Chang,Window Architecture for Deblocking Filter in H.264/AVC,in the 6th IEEE International Symposium on Signal Processing and Information Technology,August 27-30, 2006, Vancouver, Canada. (EI)
Kuo-Su Hsiao and Chung-Ho Chen,An Efficient Wakeup Design for Energy Reduction in High-Performance Superscalar Processors,in the ACM SIGMicro International Conference on Computing Frontiers (CF) ,2005, Italy. (EI)
Chung-Ming Chen and Chung-Ho Chen,A Memory Efficient Architecture for Deblocking Filter in H.264 Using Vertical Processing Order,in the IEEE International Conference on Intelligent Sensors, Sensor Networks, and Information Processing (ISSNIP),2005, Australia.
Chung-Ming Chen and Chung-Ho Chen,Parallel Processing for Deblocking Filter in H.264/AVC,in the International Conference on Communications, Internet and Information Technology (CIIT),2005, Cambridge, USA. (EI)
Chung-Ming Chen and Chung-Ho Chen,Alternative Processing Order with Efficient Architecture for Adaptive Deblocking Filter in H.264/AVC,in the International Conference on Communications, Internet, and Information Technology (CIIT),2005, Cambridge, USA. (EI)
Chung-Ming Chen and Chung-Ho Chen,An Efficient Architecture for Deblocking Filter in H.264/AVC Video Coding,in the International Conference on Computer Graphics and Imaging (CGIM),2005, Honolulu, Hawaii, USA. (EI)
Chung-Ming Chen and Chung-Ho Chen,An Efficient VLSI Architecture for Edge Filtering in H.264/AVC,in the International Conference on Circuits, Signals, and Systems,2005, Marina del Rey, CA, USA.
F.-M Huang and C.-H. Chen,Memory Access Scheduling and Bank Precharge Strategies,in the poster proceeding of 12 th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems,2004, Netherlands.
Wei-Cheng Lin and Chung-Ho Chen,An Energy-Delay Efficient Power Management Scheme for Embedded System in Multimedia Applications,in Proceedings of The IEEE Asia Pacific Conference on Circuit & System (APCCAS),2004, Taiwan. (EI)
N.-Y. Ker, and C.-H. Chen,An Effective SDRAM Power Mode Management Scheme for Performance and Energy Sensitive Embedded Systems,in the Proceeding of Asia and South Pacific Design Automation Conference (ASP-DAC) ,2003, Japan.
M.-C. Chen, I.–J. Huang, and C.-H. Chen,Parameterized MAC Unit Implementation,in the Proceeding of Asia and South Pacific Design Automation Conference,2001, Japan.
C.-H. Chen, M. -.H Sheu, M.-D. Shieh, T.-S, Li, and M.-T. Chen,Design and Implementation of a 10/100 Mbps Ethernet Switching Hub Controller,in the Proceeding of the IEEE Asia Pacific Conference on Communications,1998, Singapore.
Ming-Hwa Sheu, Chung-Ho Chen, Ming-Der Shieh and Tzung-Shiue Li,A High Performance VLSI Architecture Design for 10M /100Mbps Ethernet Switching Fabric,in the Proceeding of International Conference on Consumer Electronics,1998, USA. (EI)
C. -H. Chen and A. Wu,Microarchitecture Support for Improving the Performance of Load Target Prediction,in the Proceeding of 30 th Annual IEEE/ACM International Symposium on Microarchitecture,December 1-3, 1997, Research Triangle Park, NC, USA. (EI)
C. -H. Chen and A. Wu,An Enhanced DLX-based Superscalar System Simulator,in the 3rd Annual Workshop on Computer Architecture Education,February, 1997, San Antonio, Texas, USA.
C. -H. Chen and A. Wu,An Enhanced DLX-based Superscalar System Simulator,in the IEEE Computer Architecture Newsletter,pp.25-31, September, 1997.
C. -H. Chen and A. K. Somani,A Unified Architectural Tradeoff Methodology,in the Proceeding of the 21st International Symposium on Computer Architecture,pp. 348-357, April 18-21, 1994, Chicago, USA. 國科會甲種研究獎 (EI)
C. -H. Chen and A. K. Somani,A Cache Protocol for Error Detection and Recovery in Fault-Tolerant Computing Systems,in the 24 th International Symposium on Fault-Tolerant Computing,pp. 278-287, June 15-17, 1994, Austin Texas, USA. 國科會甲種研究獎 (EI)
R. M. Haralick, Y-H, Yao, L. G. Shapiro, I. T. Phillips, A. K. Somani, J. N. Hwang, M. Harrington, C. Wittenbrink, C. -H. Chen, X. Liu, and S. Chen,Proteus: Control and Management System,in the Proceedings of Workshop on Computer Architectures for Machine Perception,pp. 101-108, December 15-17, 1993, New Orleans, USA.
C. -H. Chen and A. K. Somani,Error Detection and Recovery in Fault-Tolerant Processor Systems Using Caches,in Proceeding of the ISMM International Conference on Parallel and Distributed Computing and Systems,pp. 388-393, 1992, Pittsburgh, PA, USA.
C. -H. Chen and A. K. Somani,Fault-Tolerant Parallel Processing with Real-Time Error Detection and Recovery,in Proceeding of the 26th Asilomar Conference on Signals, Systems & Computers,pp. 994-998, 1992, USA.
C. -H. Chen and A. K. Somani,Effects of Cache Traffics on Shared-Bus Multiprocessor Systems,in Proceedings of the International Conference on Parallel Processing,pp. I285-I288, 1992, USA. (EI)
Haralick-R-M. Somani-A-K. Wittenbrink-C. Johnson-R. Cooper-K. Shapiro-L-G. Phillips-I-T. Hwang-J-N. Cheung-W. Yao-Y-H. Chen-C-H . Yang-L. Daugherty-B. Lorbeski-B. Loving-K. Miller-T. Parkins-L. Soos-S.Proteus: a reconfigurable computational network for computer vision,Published by: IEEE Comput. Soc. Press. In Proceedings. 11th IAPR International Conference on Pattern Recognition.pp. 43-54, The Hague, Netherlands, 1992. (Judged among the 6 best papers).
Haralick-R-M. Somani-A-K. Wittenbrink-C. Johnson-R. Cooper-K. Shapiro-L-G. Phillips-I-T. Jenq-Neng-Hwang. Cheung-W. Yung-Hsi-Yao. Chung-Ho-Chen . Yang-L. Duagherty-B. Lorbeski-B. Loving-K. Miller-T. Parkins-L. Soos-S.Proteus: a reconfigurable computational network for computer vision,in Proceedings of the SPIE - The International Society for Optical Engineering, vol.1659. pp. 54-76. 1992. Conf. Title: Image Processing and Interchange: Implementation and Systems, San Jose, CA, USA. SPIE. IS\&T. 12-14 Feb. 1992. (EI)
C. M. Wittenbrink, A. K. Somani, and C. -H. Chen,Cache Write Generate for High Performance Parallel Processing,Abstract presented in the 19 th International Symposium on Computer Architecture,1992, USA. (EI)
A. K. Somani, C. Wittenbrink, R. M. Haralick, L. G. Shapiro, J. N. Hwang, C. -H. Chen, R. Johnson, and K. Cooper,Proteus System Architecture and Organization,in the Proceeding of the Fifth International Parallel Processing Symposium,pp. 287-294, 1991.
Yi-Ying Tsai, Ke-Jia Lee, and Chung-Ho Chen,Code Compression Architecture for Memory Bandwidth Optimization in Embedded Systems,in the Proceeding of the International Comput
Po-Kai Chan, Chung-Ho Chen, and Cheng-Yeh Yu,An iWARP-Based TCP/IP Offload Engine,in the Proceeding of the 17th VLSI Design/CAD Symposium,August 8-11, 2006.
W.-Z. Lin, and C.-H. Chen,10/100/1000 Mbps Ethernet MAC with Clock Management for AMBA System,in the Proceeding of the 13th VLSI Design/CAD Symposium,2002
盧偉聖、陳中和、蔡宜穎、林宇峰,特效光源之數位控制核心技術之研製,in the Proceeding of Taiwan Power Electronic Conference,2002
C.-H. Chen, M.-D. Shieh, and Jimmy Shou,VLSI Architecture of an Instruction-Based Crypto Coprocessor,in the Proceeding of the 11th VLSI Design/CAD Symposium,2000
伍麗樵 , 黃胤傅 , 陳中和 , 陳惠淳 , 陳世仁 , 陳肇男 , 方志強 ,Download On Demand 多媒體影片租借系統之實作 ,第 15 屆全國技術及職業教育研討會論文集,pp. 171-179, 2000.
S.-H. Sheu, C.-H. Chen, and T.-S Li,The Shared Bus Architecture Design and Chip Implementation for a 10M /100Mbps Ethernet Switching Fabric,in the Proceeding of the 8th VLSI
J.-S. Lin, C.-H. Chen , C.-Y. Lin, and S.-H. Liu,The Application of Fuzzy Hopfield Neural Network for Vector Quantization in Image Compression,in the Proceeding of the fifth
