國立成功大學電機工程學系 教師個人頁面
English Version
李昆忠 特聘教授
地址
奇美系館5樓95503室
Email
TEL
06-2757575 ext.62371
實驗室網站連結
積體電路測試實驗室
(R95502/ext.(06)2763881)
學經歷
學歷
1991
美國南加州大學電機博士 Ph.D., Univ. of Southern California, U.S.A.
1986
美國愛荷華大學電機碩士 M.S., University of Iowa, USA.
1981
國立臺灣大學電機學士 B.S., National Taiwan University, R. O. C.
經歷
1991 ~ 1997
國立成功大學電機系副教授
1997-present
國立成功大學電機系教授
2003/8~2004/1
美國史丹福大學訪問教授
2008~2010
台灣積體電路設計學會理事長(TICD)
2008/8~2010/7
國立成功大學晶片系統研發中心主任
2011/1~2011/12
國家實驗研究院晶片系統設計中心(CIC)兼任研究員
2011~2012
NSOC國家型計畫專案召集人
2013~2014
智慧電子國家型計畫科技部召集人
2014~2016
亞洲測試會議指導委員會主席
2017~2021
國際測試會議亞洲會議指導委員會主席
2018/1~present
國立成功大學特聘教授
研究領域
  • 超大型積體電路設計與測試 VLSI Design and Testing
  • 硬體安全 Hardware Security
  • 超大型積體電路電腦輔助設計 VLSI Computer-Aided Design
  • 計算機演算法 Computer Algorithms
  • 超大型積體電路易測性設計與內建式自我測試VLSI Testable Design and Built-in Self Test
著作
期刊論文( Journal )
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  1. Z.-W. Lai, P.-H. Huang, K.-J. Lee, “Using Both Stable and Unstable SRAM Bits for the Physical Unclonable Function,” Accepted, Journal of Electronic Testing, Theory and Applications (JETTA), Sep., 2022.
  2. K.-J. Lee, Z.-W. Lu and S.-J. Yeh, “A Secure JTAG Wrapper for SoC Testing and Debugging,” vol. 10, pp. 37603-37612, IEEE Access, 2022.
  3. C.-S. Ye, S.-X. Zheng F.-J. Tsai, C. Wang, K.-J. Lee, W.-T. Cheng, S. M. Reddy, J. Zawada, M. Kassab, J. Rajski, “Efficient Test Compression Configuration Selection,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, .41, issue 7, pp. 223-2336, July, 2022.
  4. K.-J. Lee, C.-H. Wu, and T.-Y. Hou, “An efficient procedure to generate highly compact diagnosis patterns for transition faults,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems,vol. 41, issue 3, pp. 737-749, Mar. 2022.
  5. K.-J. Lee, C.-A. Liu and C.-C. Wu, “A Dynamic Key Based Secure Scan Structure for Manufacturing and In-Field IC Testing,” IEEE Trans. Emerging Topics in Computing, vol. 10, no. 1, pp. 373-385, Mar. 2022.
  6. Y.-H. Chen, C.-M. Hsu, and K.-J. Lee, “Test Chips with Scan-Based Logic Arrays,” IEEE Trans. Very Large Scale Integration Systems, vol. 40, no. 4, pp 790-802, Apr. 2021.
  7. Y.-C. Kung, K.-J. Lee, and S. M. Reddy, “Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems. vol.39, no. 6. pp. 1340-1345, 2020.
  8. C.-H. Wu, K.-J. Lee, S. M. Reddy, “An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test-Compaction,” IEEE Trans. Very Large Scale Integration Systems. vol. 27, no. 9, pp. 2105~2118, 2019.
  9. K.-J. Lee, B.-R. Chen, and M. A. Kochte, “On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Scan Chains,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.38, no. 2, pp. 309-321, Feb., 2019.
  10. C.-H. Wu, S.-L. Lin, K.-J. Lee and S.M. Reddy, “A Repair-for-Diagnosis Methodology for Logic Circuits,” IEEE Transactions on Very Large Scale Integration Systems, vol.26, no.11, pp.2254-2267, Nov., 2018.
  11. C.-W. Wu, K.-J. Lee, and A. P. Su, “A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip,” IEEE Trans. Computers, vol. 67, no. 9, pp.1231-1245, Sep., 2018.
  12. W.-H. Hsu, M. A. Kochte, and K.-J. Lee, “Built-In Test and Diagnosis for TSVs with Different Placement Topologies and Crosstalk Impact Ranges,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 6, pp. 1004-1017, June 2017.
  13. J.-Z. Chen and K.-J. Lee, “Test Stimulus Compression Based on Broadcast Scan with One Single Input,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 1, pp. 184-197, Jan. 2017.
  14. K.-K. Liu, W.-H Hsu, and K.-J. Lee, “A high-performance SoC debug platform,” Smart Science, vol 3, no 4, pp.202-208, 2015.
  15. W.-C Lien, K.-J. Lee, K. Chakrabarty, and T.-Y. Hsieh,Efficient LFSR reseeding based on internal-response feedback,Journal of Electronic Testing: Theory and Applications (JETTA), vol. 30, no. 6, pp. 673-685 ,Dec. 2014.
  16. Chang, C. Y., & Lee, K. J. On Deadlock Problem of On-Chip Buses Supporting Out-of-Order IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 22(3), 484-496, Mar. 2014.
  17. H. Li, W.-C. Lien, I.-C. Lin, K.-J. Lee, Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol 33, no. 1, pp.127-138, Jan. 2014.
  18. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, and W.-L. Ang,An efficient on-chip test generation scheme based on programmable and multiple twisted-ring counters, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 8, pp. 1254-1264,Aug. 2013
  19. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, K. Chakrabarty and Y.-H. Wu, “Counter-Based Output Selection for Test Response Compaction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 1, pp. 152-164, Jan. 2013.
  20. K.. J. Lee, T.-Y.Hsieh and M. A. Breuer, "Efficient over-detection elimination of acceptable faults for yield improvement, "IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems", Vol. 31,NO. 5,pp. 754-764,May, 2012"
  21. K.-J. Lee, W.-C. Lien and T.-Y. Hsieh, “Test Response Compaction via Output Bit Selection," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 10, Oct. 2011.
  22. T.-Y. Hsieh, K.-J. Lee and M. A. Breuer, "An error-tolerance-based test methodology to support product grading for yield enhancement," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 6, pp. 930-934, Jun. 2011.
  23. C.-M. Huang, C.-M. Wu, C.-C. Yang, S.-L. Chen, C.-S. Chen, J.J. Wang, K.J. Lee, and C.L. Wey, “Programmable System-on-Chip (SoC) for Silicon Prototyping,” IEEE Transactions on Industrial Electronics, Vol. 58, No. 3, March, 2011.
  24. K.J. Lee, Tong-Yu Hsieh, and Ching-Yao Chang, “On-Chip SOC Test Platform Design Based on IEEE 1500 Standard,” IEEE Transactions on Very Large Scale Integration Systems, 18(7), 1134-1139, 2010.
  25. Tai-Hua Lu, Chung-Ho Chen, and K.J. Lee, “Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores,” IEEE Transactions on Very Large Scale Integration Systems, pp. 1-5, 2009.
  26. L.-T. Wang, R. Apte, S. Wu, B. Sheu, and K.J. Lee, X. Wen, W.-B. Jone, W.-S. Wang, H.-J. Chao, J. Guo, J. Liu, Y. Niu, Y.-C. Sung, C.-C. Wang, and F. Li, “Turbo1500: Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard,” IEEE Design & Test of Computers, 26(1), pp. 26-35, 2009.
  27. T.-Y. Shieh, K.J. Lee, and M.A. Breuer, “An Error-Rate Based Test Methodology to Support Error-Tolerance,” IEEE Trans. Reliability, 57(1), pp. 204-214, Jan, 2008.
  28. K.J. Lee, C.-M. Huang, C.-C. Yang, C.-M. Wu, and J.-Y. Jou, “Multi-Project System-on-Chip (MP-SoC): A Novel Cost-Efficient Silicon Prototyping Service for Academic SoC Designs,” Innovations 2007: World Innovations in Engineering Education and Research, pp. 391-400, 2007.
  29. W.-C. Huang, K.J. Lee, C.-Y. Chang, and Y.-H. Wu, “DASTEP: A design automation system for SOC test platform,” Int’l Journal on Electrical Engineering, Vol.14, No. 3, pp. 219-227, June 2007. (EI)
  30. T.-Y. Shieh, K.J. Lee, and M.A. Breuer, “Preventing over-detection of acceptable faults for yield enhancement,” Int’l Journal on Electrical Engineering, Vol. 14, No. 3, pp. 185-193, June 2007.(EI)
  31. T.C. Huang and K.J. Lee. A hybrid LFSR design for low power applications. Journal of Chinese Institute of Electrical Engineering, Vol. 10, No. 1, pp. 1-8, Feb. 2003.
  32. J.J. Chen, J.K. Yung and K.J. Lee. Test Pattern Generation & Clock Disabling for Simultaneous Test Time and Power Reduction. IEEE Trans. on CAD, Vol. 22, No. 3, pp. 363-370, Mar., 2003.
  33. T.C. Huang and K.J. Lee. An Interleaving technique for reducing peak power in multiple chain scan circuits during test applications. Journal of Electronic Testing, Theory and Applications (JETTA), Vol.18, No.6, pp. 627-636, Dec. 2002.
  34. W.B. Jone, D.C. Huang, S.C. Wu and K.J. Lee. An efficient BIST method for small buffers. IEEE Trans. on VLSI Systems, Vol. 10, No. 4, pp. 512-515, Aug. 2002.
  35. Wei-Lun Wang and K.J. Lee. An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment. Journal of Electronic Testing, Theory and Applications (JETTA), Vol.18, No.1, pp. 43-53, Feb. 2002.
  36. Yue-Che Wen and K.J. Lee. A Current-Mode BIST Structure of DACs. Journal of the International Measurement Confederation (IMEKO), Measurement 31, pp. 147-163, 2002.
  37. K.J. Lee and Wei-Chiang Wang. A 0.5μm concurrent testable chip of a fifth-order gm-C filter. Analog Integrated Circuits and Signal Processing, Vol. 32, pp. 231-247, 2002.
  38. W.L. Wang and K.J. Lee. An on-chip March pattern generator for testing embedded memory cores. IEEE Trans. on VLSI Systems, Vol. 9, No. 5, pp. 730-735, Oct. 2001.
  39. K.J. Lee and Cheng-I Huang. A hierarchical test control architecture for SOC design. Journal of Chinese Institute of Electrical Engineering, Vol. 8, No. 4., pp. 355-364, 2001.
  40. Wei-Lun Wang and K.J. Lee. Fast deterministic test pattern generation for scan-based BIST environment. Journal of Chinese Institute of Electrical Engineering, Vol. 8, No. 4., pp. 365-376, 2001.
  41. K.J. Lee and T.C. Huang. Reduction of power consumption in scan-based circuits during test application by an input control technique. IEEE Trans. on CAD, Vol. 20, No. 7, pp. 911-917, July, 2001.
  42. T.C. Huang and K.J. Lee. Token scan cell for low power testing, IEE Electronics Letters, Vol.37, No.11, pp. 678-679, May 2001.
  43. Yun-Che Wen and K.J. Lee. Analysis and generation of control and observation structures for analog circuits. IEEE Trans. on CAD, Vol.20, No.1, pp. 165-171, Jan., 2001.
  44. S.C. Chang, K.J. Lee, Zhong-Zhen Wu and Wen-Ben Jone. Reducing test application time by scan flip-flops sharing. IEE Proceedings on Computers and Digital Technology, Vol. 147, pp. 42-52, Jan. 2000.
  45. K.J. Lee, On the testing of semiconductor memory, Engineering Science & Technology Bulletin of NSC, No. 43, pp. 38-41, Jan. 2000.
  46. K.J. Lee, J.J. Chen and C.H. Huang. Broadcasting test patterns to multiple circuits. IEEE Trans. on CAD, Vol.18, No.12, pp. 1793-1802, Dec., 1999.
  47. K.J. Lee, Wei-Chung Wang and Kuo-Shung Huang. A current-mode testable design of OTA-C filters. IEEE Trans. on Circuits and Systems-II, Vol.46, No.4, pp. 401-413, April, 1999.
  48. K.J. Lee, J.J. Tang, T.C. Huang. BIFEST: An Intermediate Fault Effect Sensing and Test Generation System for CMOS Bridging faults. ACM Trans. on Design Automation of Electronic Systems, pp. 194-218, April, 1999.
  49. K.J. Lee and Cheng-Hsuing Kuo. Concurrent error detection, diagnosis, and fault tolerance for switched-capacitor filters, Journal of Information Science and Engineering, Vol.14, No.4, pp. 863-890, Dec. 1998.
  50. J.J. Tang, K.J. Lee and B.D. Liu. A new representation for PLA to facilitate testing and logic design. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.17, No.10, pp. 1030-1043, Oct. 1998.
  51. K.J. Lee, Wei-Lun Wang and Jhing-Fa Wang. A general structure of feedback shift registers for built-in self test. Journal of Information Science and Engineering, Vol.14, No.3, pp. 645-667, Sep. 1998.
  52. Yun-Che Wen and K.J. Lee. BIST structure for DAC testing. IEE Electronics Letters, Vol.34, No.12, pp.1173-1174, Jun. 1998.
  53. K.J. Lee and J.J. Tang. A built-in current sensor based on current-mode design. IEEE Trans. on Circuits & Systems, Part II, Vol.45, No.1, pp. 133-137, Jan. 1998.
  54. K.J. Lee, Yun-Che Wen. Two novel control and observation structures for Analog circuits. IEE Electronics Letters, Vol.33, No.19, pp.1590-1592, Sep. 1997.
  55. K.J. Lee, Kuo-Shung Huang and Wei-Chung Wang. A concurrent test method for OTA-C filters. IEE Electronics Letters, Vol.33, No.1, pp. 1-2, Jan. 1997.
  56. K.J. Lee, Kuo-Shung Huang and Min-Cheng Huang. Design of low voltage built-in current sensors. IEE Electronics Letters, Vol.32, No.21, pp. 1942-1943, Oct. 1996.
  57. K.J. Lee. IDDQ testing: a new IC testing method (Invited). Electronic Magazine, No.16, pp. 60-65, Nov. 1996.
  58. K.J. Lee, Tian-Pao Lee, Rong-Chang Wen and Zhi-Yi Lin. Analogue boundary scan architecture for DC and AC testing. IEE Electronics Letters, Vol.32, No.8, pp. 704-705, Apr.11, 1996.
  59. K.J. Lee, Chih-Nan Wang, R. Gupta, and M.A. Breuer. An integrated system for assigning signal flow directions to CMOS transistors. IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, Vol.14, No.12, pp. 1445-1458, Dec. 1995.
  60. J.J. Tang, K.J. Lee and B.D. Liu. A practical current sensing technique for IDDQ testing. IEEE Trans. on VLSI Systems, Vol.3, No.2, pp.302-310, June, 1995.
  61. K.J. Lee, C.A. Njinda, and M.A. Breuer. SWiTEST: A switch level test generation system for CMOS combinational circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.13, No.5, pp.625-637, May 1994.
  62. K.J. Lee and M.A. Breuer. Design & test rules for CMOS circuits to facilitate IDDQ testing to detect bridging faults. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.11, No.5, pp.659--670, May 1992.
會議論文( Conference )
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  1. D.-Y. Chen, C.-H. Lee, K.-J. Lee, N.-H Tsend, H.W. Hung, and H.-Y Yang, “An On-Chip High-resolution Delay Measurement Scheme for TSVs in 3DIC,” Asia Pacific Conf. on Circuits & Systems, 2024.
  2. Y.-C. Lin, and K.-J. Lee, “A Lightweight Memory Protection Scheme with Criticality-Aware Encryption and Embedded MAC for Secure DNN Accelerators, Asia Pacific Conf. on Circuits & Systems, 2024.
  3. P.-W. Chen, K.-J. Lee, “Test Chip Design for Small Delay Defects Based on C-testable Arrays and Mutually Orthogonal Latin Squares,” VLSI DESIGN/CAD Symp, 2024.
  4. D.-Y. Chen, K.-J. Lee, N.-H. Tseng, H.-W. Hung, and H.-Y. Yang, “An On-chip High-resolution & High-accuracy Delay Measurement Scheme for TSVs in 3DIC,” VLSI DESIGN/CAD Symp, 2024.
  5. H.Y. Chen, K.-Y. Peng and K.-J. Lee, “A Novel Unified Modular Arithmetic Unit for Elliptic Curve Cryptography,” Intl’ VLSI Symp. Technology, Systems and Applications, 2023.
  6. S.-C. Yeh, K.-J. Lee and D.-Y. Chen, “An Authentication-Based Secure IJTAG Network,” Asian Test Symposium 2022.
  7. Y.-F. Chen, D.-Y. Kang and K.-J. Lee, “Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks,” Int’l Test Conf. 2022.
  8. D.-Y. Kang, S.-N. Lin and K.-J. Lee, “Diagnosing Transition Delay Faults under Scan-Based Logic Array,” Int’l Test Conf. in Asia, 2022.
  9. S.-X. Zheng, C.-Y. Yeh, K.-J. Lee, C. Wang, W.-T. Cheng, M. Kassab, J. Rajski, S. M. Reddy, “Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations,” VLSI Test Symposium, 2022.
  10. H.-Y. Chi and K.-J. Lee, “Lightweight Hardware-Based Memory Protection Mechanism on IoT Processors,” IEEE Asian Test Symp., 2021.
  11. S.-X. Zheng, C.-S. Ye, K.-J. Lee, “Pattern Count Estimation and Optimum Configuration Selection for Test Compression Configurations in Scan-Based Design,” VLSI Test Technology Workshop, 2021, Best paper award.
  12. F.-J. Tsai, C.-S. Ye, Y. Huang, K.-J. Lee, W.-T. Cheng, S. M. Reddy, M. Kassab, J. Rajski, S.X. Zheng, “Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channels Configurations,”IEEE International Test Conference (ITC), 2020.
  13. F.-J. Tsai, C.-S. Ye, Y. Huang, K.-J. Lee, W.-T. Cheng, S. M. Reddy, M. Kassab, J. Rajski, S.X. Zheng, “Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels,”IEEE International Test Conference in Asia (ITC-Asia), 2020.
  14. K.-J. Lee, et al., High Security and Low Power Integrated Circuits and Systems for IoT Design and Analysis, VLSI DESIGN/CAD Symp, 2020.
  15. F.-J. Tsai, C.-S. Ye, Y. Huang, K.-J. Lee, W.-T. Cheng, S. M. Reddy, M. Kassab, J. Rajski, S.-X. Zheng, “Prediction of Test Data Volume for Scan Architectures with Different Input Commpression Ratio, VLSI Test Technology Workshop, 2020.
  16. F.-J. Tsai, C.-S. Ye, Y. Huang, K.-J. Lee, W.-T. Cheng, S. M. Reddy, M. Kassab, J. Rajski, “Efficient Prognostication of Pattern Count with Different Input Compression Ratios,” European Test Symp., May, 2020.
  17. C-H. Wu, Y. Huang, K.-J. Lee1, W.-T. Cheng2, G. Veda, S. M. Reddy, C.-C. Hu, C.-S. Ye, “Deep learding based test compression analyzer,”Asian Test Symp. 2019.
  18. M.-H. Kuo and K.-J. Lee, “Time-Related Hardware Trojan Attacks on Processor Cores,”Int’l Test Conf. in Asia, 2019.
  19. M.-H. Kuo and K.-J. Lee, “Designing Time-Based Hardware Trojans,”VLSI Test Technology Workshop, 2019.
  20. C.-J. Shang, C.-H. Wu, K.-J. Lee, and Y.-H. Chen, “A Novel Test Generation Method for Small Delay Defects with User-Defined Fault Model,”, IEEE Int’l VLSI Symp. on Design, Automation and Test, 2019.
  21. Y.-C. Kung, K.-J. Lee, S. M. Reddy, “Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run, IEEE International Test Conference (ITC), pp. 1-10, 2018.
  22. C.-C. Wu, M.-H. Kou, K.-J. Lee,  “A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks,” IEEE Asian Test Symposium (ATS), pp. 48-53, 2018. 
  23. Y.-C. Kung, K.-J. Lee, and S. M. Reddy, “Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run,”IEEE International Test Conference in Asia (ITC-Asia), pp. 1-6, 2018.
  24. Y.-C. Kung, K.-J. Lee and S.M. Reddy,“Compact Test Pattern Generation for Stuck-at Faults and Transition Faults,”in Proc., VLSI Test Technology Workshop, 2018.
  25. C.-H. Wu, K.-J. Lee and S.M. Reddy, “Test generation for open and delay faults in CMOS circuits,” IEEE International Test Conference in Asia, PP. 21-26, 2017.
  26. C.-H. Chen, Y.-C Kong and K.-J. Lee, “Test Compression with Single-Input Data Spreader and Multiple Test Sessions,” Page 28-33, Asian Test Symposium, 2017.
  27. S.-L. Hong and K.-J. Lee, “A Run-Pause-Resume Silicon Debug Technique with Cycle Granularity for Multiple Clock Domain Systems,” IEEE Int’l Test Conference, Page 1 – 10, 2017.
  28. C.-H. Wu, K.-J. Lee and S. M. Reddy, “Test Generation for Open and Delay Faults in CMOS Circuits,” IEEE Int’l Test Conference in Asia, Paper C1-2, 2017.
  29. K.-J. Lee, P.-H. Tang, M. A. Kochte and B.-R. Chen, “An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains, VLSI DESIGN/CAD Symp, 2017.
  30. S.-L. Hong and K.-J. Lee, “A Silicon Debug Technique for Multiple Clock Domain Systems,” VLSI Test Technology Workshop, Paper S1-2, 2017.
  31. S.-L. Hong and K.-J. Lee, “A Run-Pause-Resume Silicon Debug Technique for Multiple Clock Domain Systems,” IEEE Int’l Test Conference in Asia, pp.46-51, 2017.
  32. H.-P. Kuo, A. P. Su and K.-J. Lee, “A Low Power Synthesis Flow for Multi-Rate Systems,” Paper D6.1, IEEE Int’l VLSI Symp. on Design, Automation and Test, pp. 1-4, 2017.
  33. S.-L. Lin, C.-H. Wu, K.-J. Lee, “Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis,” Paper 1B.1, Asia Test Symposium, 2016.
  34. W.-C. Lien and K.-J. Lee, “Output Bit Selection Methodology for Test Response Compaction,” Paper TC.2, IEEE Int’l Test Conf., 2016
  35. C. H. Wu, S. J. Lee and K. J. Lee, "Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults," Asia and South Pacific Design Automation Conference, 2016
  36. C. M. Shiao, W. C. Lien and K. J. Lee, "A Test-per-cycle BIST architecture with low area overhead and no storage requirement," International Symposium on VLSI Design, Automation and Test, 2016
  37. K.-J. Lee, P.-H. Tang and M. A. Kochte, “An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains,” Paper 16.3, IEEE Int’l Test Conf., 2016
  38. C.-H. Wu, K.-J. Lee, “Transformation of Multiple Fault Models to a Unified Model for ATPG Efficiency Enhancement,” Paper 16.1, IEEE Int’l Test Conf., 2016
  39. J.-C. Ye, M. A. Kochte, K.-J. Lee, and H-J. Wunderlich, “A High-Efficiency 3D-IC Test Architecture with IEEE Std. 1687, Post-E, VLSI DESIGN/CAD Symp., 2016
  40. C.-H. Wu, K.-J. Lee, “An Efficient Test Pattern Generation Method for Cell-Internal Faults,” VLSI DESIGN/CAD Symp., Paper S5-2, 2016. (Best paper award)
  41. S.-L. Lin, C.-H. Wu, K.-J. Lee, “Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis,” VLSI Test Technology Workshop, 2016
  42. W.-H. Hsu, M. A. Kochte, and K.-J. Lee, “3D-IC Test Architecture for TSVs with Different Impact Ranges of Crosstalk Faults,” IEEE Int’l VLSI Symp. on Design, Automation and Test, 2016
  43. J.-C. Ye, M. A. Kochte, K.-J. Lee, and H-J. Wunderlich, “Autonomous Testing for 3D-ICs with IEEE Std. 1687,” Paper 5C.1, Asian Test Symposium, 2016.
  44. L.-Y. Lu, C.-Y. Chen, Z.-H. Chen, B.-T. Yeh, T.-H. Lu, P.-Y. Chen, P. H. Tang, K.-J. Lee, L.-Y. Chiou, S.-J. Chang, C.-H. Tsai, C.-H. Chen, and J.-M. Lin, “A Testable and Debuggable Dual-Core System with Thermal-Aware Dynamic Voltage and Frequency Scaling,”IEEE Asia and South Pacific Design Automation Conference, 2016.
  45. C.-H. Wu, S. J. Lee and K.-J. Lee, “Test and Diagnosis Pattern Generation for Dynamic Bridging Faults and Transition Delay Faults,” IEEE Asia and South Pacific Design Automation Conference, 2016
  46. C.-H. Wu, K.-J. Lee and S.-T. Wang, “Diagnosis Pattern Generation to Distinguish Inter-Gate and Intra-Gate Faults in CMOS Logic Circuits,”IEEE Workshop of Register-Transfer and High Level Testing, S1.4, 2015.
  47. C.-M. Shiao, W.-C. Lien and K.-J. Lee A Circular BIST Architecture Using Internal Responses of Circuits for Reseeding and Extra Observation, IEEE Workshop of Register-Transfer and High Level Testing, S4.3, 2015.
  48. C.-H. Wu, S. J. Lee and K.-J. Lee, “Distinguishing Dynamic Bridging Faults and Transition Delay Faults,”IEEE Int’l Conf. on ASIC.
  49. C.-H. Wu, K.-J. Lee, and S.-T. Wang, “Diagnosis pattern generation for inter-gate and intra-gate faults in CMOS circuits,” VLSI DESIGN/CAD Symp., Paper S14-1, 2015.
  50. C.-H. Wu, K.-J. Lee, “An efficient diagnosis pattern generation method for stuck-at-faults with high test compaction,” VLSI DESIGN/CAD Symp., Paper S02-5, 2015. (Best paper award)
  51. C.-H. Wu, K.-J. Lee, and S.-T. Wang, “Diagnosis pattern generation to distinguish transition delay faults and transistor stuck-open faults,” VLSI Test Technology Workshop, Paper S1.1, 2015 (Best paper award).
  52. C.-H. Wu, and K.-J. Lee, “Improve Transition Fault Diagnosability Via Observation Point Insertion,” IEEE Int’l VLSI Symp. on Design, Automation and Test, 2015.
  53. H.-C. Chen, C.-R. Wu, K. S.-M. Li, and K.-J. Lee, “A Breakpoint-Based Silicon Debug Technique with Cycle-Granularity for Handshake-Based SoC,” IEEE Design, Automation and Test in Europe, pp. 1281-1284, 2015.
  54. Li, L.C., Hsu, W. H., Lee, K. J., & C. L. Hsu, An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. In 20th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 520-525, 2015.
  55. W.-C. Lien, K.-J. Lee, K. Chakrabarty, T.-Y. Hsieh, and C.-H. Wu, “Compression of test response with many unknown values using multiple counters,” VLSI DESIGN/CAD Symp., Paper S15-4, 2014.
  56. Y.-D. Wang, and K.-J. Lee, “Efficient Diagnosis Pattern Generation for Transition Faults Using Combinational Circuit Model,” IEEE Workshop of Register-Transfer and High Level Testing, pp. I.4.S, 2014.
  57. W.-C. Lien, K.-J. Lee, K. Chakrabarty, and T.-Y. Hsieh, “Output-Bit Selection with X-Avoidance using Multiple Counters for Test-Response Compaction, IEEE European Test Symp., May 2014.
  58. Y.-D. Wang, and K.-J. Lee, “Efficient Diagnosis Pattern Generation for Transition Faults Using Combinational Circuit Model,” invited paper, IEEE Int’l Conf. Solid-State Integrated Circuit Technology, 2014.
  59. C.-H. Wu, K.-J. Lee, and W.-C. Lien, “An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model,” IEEE VLSI Test Symp., pp. 240-245, 2014.
  60. C.-H. Wu, and K.-J. Lee, “An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults,” IEEE Asian Test Symp. pp. 306-311,, 2014.
  61. C.-H. Wu, K.-J. Lee, and W.-C. Lien, “An efficient stuck-at-fault diagnosis model using a single circuit model,” VLSI DESIGN/CAD Symp., Paper S15-1, 2014.
  62. W.-C. Lien, K.-J. Lee, K. Chakrabarty, and T.-Y. Hsieh, “Output Selection for Test Response Compaction Based on Multiple Counters,” IEEE Int’l VLSI Symp. on Design, Automation and Test., pp. DR112, Apr. 2014.
  63. C.-H. Wu, K.-J. Lee, and W.-C. Lien, “An efficient diagnosis pattern generation procedure,” VLSI Test Technology Workshop, Paper S1.1, 2014.
  64. Lee, K. J., & Wu, C. H. (2014, October). An efficient diagnosis-aware pattern generation procedure for transition faults. In IEEE International Test Conference (ITC), pp. 1-10, 2014.
  65. H.-C. Chen, K. S.-M. Li, and K.-J. Lee, “A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SOC,” IEEE Workshop of Register-Transfer and High Level Testing, pp. I.4.S, 2013.
  66. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, and K. Chakrabarty, “A new LFSR reseeding scheme via internal response feedback,” IEEE Asian Test Symp. pp. 6B-3, 2013.
  67. W.-C. Lien and K.-J. Lee, “Output Bit Selection Methodology for Test Response Compaction,” IEEE Design Automation Conference, 2013, pp. 1-2. (PhD Forum).
  68. K.-J. Lee, C.-Y. Chang, and H.-Y. Yang, “An Efficient Deadlock-Free Multicast Routing Algorithm for Mesh-Based Networks-on-Chip,” IEEE VLSI-DAT Symposium, Paper No. DR61, 2013 (best paper award candidate).
  69. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh and K. Chakrabarty, “A New Selection Algorithm to Avoid Unknown Responses via Counter-Based Output Selection Scheme,” The 8th VLSI Test Technology Workshop, Sec. 4, pp. 4-1, 2013.
  70. W.-C. Lien, W.-L. Ang, T.-Y. Hsieh and K.-J. Lee, “High-Performance Deterministic BIST Using Multiple Twisted-Ring Counters,” The 23th VLSI DESIGN/CAD Symposium, Sec. 15, pp. 15-5, 2012.
  71. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, K. Chakrabarty and Y.-H. Wu, “Test Response Compaction Based on a Single Counter,” The 7th VLSI Test Technology Workshop, Sec. 3, pp. 3-1, 2012. (Best Paper Award)
  72. W.-C Lien, K,-J. LEE and T.-Y. Hsieh, “Output Bit Selection for Test Response Compaction,”Int’l Conf. in Solid-State Integrated Circuit Technology(ICSICT), 2012
  73. W.-C Lien, K,-J. LEE and T.-Y. Hsieh,“A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume,” Asian Test Symposium, 2012
  74. W.-C Lien, T.-Y. Hsieh, K,-J. LEE, and K. Chakrabarty, “Accumulator-Based Output Selection for Test Response Compaction, “IEEE Int’l Symp. On Circuits and Systems, May 2012.
  75. W.-C Lien, T.-Y. Hsieh, and K,-J. LEE, “Routing-Efficient Implementation of an Internal-Response-Based BIST Architcture, “2012 VLSI-DAT Symposium,(Best Paper Award)
  76. K.-J. Lee, Alan Su, L.-F. Chen, J.-W. Jhou, Jiff Kuo, Mark Liu, “A Software/Hardware Co-Debug Platform for Multi-Core Systems” IEEE 9th International Conference on ASIC (ASICON 11), Paper 2E-2, 2011.
  77. K.-J. Lee, C.-Y. Chang and I-J. Chen, “EPIDETOX: An ESL Platform for Integrated Circuit Design and Tool Exploration,” Embedded System Week, 2011
  78. A. Su, J. Kuo, K.-J. Lee, I.-J Huang, G.-A. Jian, C.-A. Chien, J.-I. Guo, C.-H. Chen, “Multi-core software/hardware co-debug platform with ARM , on-chip test architectural and AXI/AHB bus monitor” International Symposium on VLSI Design, Automation and Test(VLSI-DAT), Page(s): 1-6, 2011
  79. W.-C. Lien, T.-Y. Hsieh, C.-T. Tsai andK.J. Lee, “A Rotation-Based BIST with Self-Feedback Logic to Achieve Complete Fault Coverage,” Int’l Symp. VLSI Design, Automation and Test, 2011, Hsinchu, Taiwan, pp. 252-255.(Best Paper Candidate)
  80. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh and S.-S. Chien, “Test Response Compaction via Accumulator-Based Output Selection,” The 22th VLSI DESIGN/CAD Symposium, 2011, Yulin, Taiwan. (Best Paper Award)
  81. W.-C. Lien, K.-J. Lee and T.-Y. Hsieh, “Concurrent Determination of Seeds and Test Sequences for LFSR Reseeding,” The 6th VLSI Test Technology Workshop, July 13-15, 2011.
  82. C.-Y. Chang, Y.-J. Chang, K.J. Lee, J.-C. Yeh, S.-Y. Lin and J.-L. Ma, “Design of On-Chip Bus with OCP Interface,” Int’l Symp. VLSI Design, Automation and Test, pages 211-214, 2010.
  83. W.C. Lien and K.J. Lee, “A Complete Logic BIST Technology with No Storage Requirement,” Asian Test Symposium, 2010, Shanghai, China, pp.129-134.
  84. W.C. Lien and K. J. Lee, “Efficient Mixed-Mode BIST for Complete Fault Coverage,” VLSI Test Technology Workshop, August 18-20, 2010.
  85. W. C. Lien, Y. T. Wang, Y. H. Wu and K. J. Lee, “Counter-Based Output Selection Method for Test Response Compaction,” Electronic Technology Symposium, June 18, 2010.
  86. T.Y. Hsieh, M.A. Breuer, M. Annavaram, S.K. Gupta and K.J. Lee, Tolerance of Performance Degrading Faults for Effective Yield Improvement, Int’l Test Conf, pp. 1-10, 2009.
  87. C.Y. Chang, C.Y. Hsiao and K.J. Lee, Transaction Level Modeling and Design Space Exploration for SOC Test Architectures, Asian Test Symposium, pp. 200-205, 2009.
  88. K.J. Lee, S.Y. Liang and Alan Su, “A Low-Cost SOC Debug Platform Based on On-Chip Test Architectures,” Int’l SOC Conf, pp. 161-164, 2009.
  89. Tong-Yu Hsieh, K.J. Lee, and M. A. Breuer, “An Efficient Multi-Phase Test Technique to Perfectly Prevent Over-Detection of Acceptable Faults for Optimal Yield Improvement via Error-Tolerance,” Int’l Symp. VLSI Design, Automation and Test, pp. 255-258, 2009.
  90. K.J. Lee, Chin-Yao Chang, Alan Su, and Si-Yuan Liang , A Unified Test and Debug Platform for SOC Design, International Conference on ASIC (ASICON), pp.577-580, 2009.
  91. Chin-Yao Chang, Chih-Yuan Hsiao, K.J. Lee and Alan Su, Transaction Level Modeling and Design Space Exploration for SOC Test Architectures, Asian Test Symposium (ATS), pp.200-205, 2009.
  92. Jing-Wun Lin, Chen-Chieh Wang , Chin-Yao Chang, Chung-Ho Chen, K.J. Lee, Yuan-Hua Chu, Jen-Chieh Yeh, and Ying-Chuan Hsiao, Full System Simulation and Verification Framework, International Conference on Information Assurance and Security (ISA), pp. 162-168, 2009.
  93. T.Y. Hsieh, K.J. Lee and Melvin A. Breuer, “Test Pattern Generation for Efficient Identification of Acceptable Chips Based on Error-Tolerance,” The 20th VLSI DESIGN/CAD Symposium, 2009.
  94. Chin-Yao Chang, Yi-Jiun Chang, K.J. Lee, Jen-Chieh Yeh, Pao-Jui Huang and Yuan-Hua Chu, "Design of OCP Wrappers and Protocal Converters for System Integration", The 20th VLSI Design/CAD Symposium, 2008.
  95. Y.-Y. Tsai, Y.-C. Lin, K.-J. Lee, C.-W. Yen, and C.-H. Chen, “A software-based test methodology for direct-mapped data cache,” IEEE Asian Test Symp. (ATS), pp. 363-368, 2008.
  96. T.-H. Lu, C.-H. Chen, and K.-J. Lee, “A hybrid self-testing methodology of processor cores,” IEEE Int’l Symp. on Circuits & Systems (ISCAS), May 18-21, 2008.
  97. L.T. Wang, R. A., S. Wu, B. Sheu, K.J. Lee, X. Wen, W.B. Jone, C.H. Yeh, W.S. Wang, H.J. Chao, J. Guo, ” Turbo1500: Toward Core-Based Design for Test and Diagnosis Using IEEE Std. 1500,” Intl Test Conf, pp. 1-9, 2008.
  98. K.J. Lee , Chin-Yao Chang and Jia-Der Wang, Constructing On-Chip Test Infra-Structure at Electronic System Level, Workshop on RTL and High Level Testing (WRTLT), 2008.
  99. C.-M. Huang, C.-M. Wu, C.-C. Yang, K.-J. Lee, and C.-L. Wey, “Programmable system-on-chip (SoC) for silicon prototyping,” IEEE Int’l Symp. Industrial Electronics, pp. 1976~1981, 2008
  100. Tong-Yu Hsieh, K.J. Lee, C.-L. Lu and M. A. Breuer, A systematic methodology to employ error-tolerance for yield improvement, International Symposium on VLSI Design, Automation and Test, pp.105-108, 2008.
  101. Chin-Yao Chang, K.J. Lee,and Jia-Der Wang, On-Chip Test Platform Design at Electronic System Level, The 19th VLSI Design/CAD Symp, 2008.
  102. Tong-Yu Hsieh, K.J. Lee, and M. A. Breuer, Chip Quality Grading to Enhance Effective Yield" ,The 2nd VLSI Test Technology Workshop, 2008.
  103. Wen-Cheng Huang, Chin-Yao Chang and K.J. Lee, Toward Automatic Synthesis of SOC Test Platforms, VLSI Design, Automation and Test, pp.156-159, 2007.
  104. Tong-Yu Hsieh, K.J. Lee and Jian-Jih You, Test Efficiency Analysis and Improvement of SOC Test Platforms, Asian Test Symposium, pp.463-466, 2007.
  105. Tong-Yu Hsieh, K.J. Lee and M. A. Breuer, Reduction of Detected Acceptable Faults for Yield Improvement via Error-Tolerance, Design, Automation and Test in Europe (DATE), pp. 1599-1604, 2007.
  106. K.J. Lee, T.-Y. Hsieh, and M. A. Breuer, Test pattern generation for a fault-oriented test methodology to improve yield based on error-tolerance, The 1st VLSI Test Technology Workshop, 2007.
  107. Tong-Yu Hsieh, K.J. Lee and Jian-Jih You, Test Efficiency Analysis of SOC Test Platforms," The 18th VLSI Design/CAD Symposium, 2007.
  108. C.-M. Huang, K.-J. Lee, C.-C. Yang, W.-H. Hu, S.-S. Wang, J.-B. Chen, C.-S. Chen, L.-D. Van, C. Wu, W.-C. Tsai, and J.-Y. Jou, “Multi-project system on-chip (MP-SoC): a novel test vehicle for SOC silicon prototyping,” IEEE Int’l SOC Conf., pp.137-140, 2006.
  109. T.-C. Huang, J.-C. Tzeng, Y.-W. Chao, J.-J. Chen, W.-T. Liu, and K.-J. Lee, “A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling,” IEEE Int’l Symp. on VLSI Design, Automation & Test, pp. 1-4, 2006.
  110. Tong-Yu Hsieh, K.J. Lee and Melvin A. Breuer, An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance, in Proc., VLSI Test Symposium, pp. 130-135, 2006.
  111. Tong-Yu Hsieh, K.J. Lee and Melvin Breuer, Maximizing Yield Improvement via Error-Tolerance by Avoiding Detection of Acceptable Faults, The 17th VLSI Design/CAD Symposium, 2006.
  112. Wen-Cheng Huang and K.J. Lee, DASTEP: A Design Automation System For System-on-Chip Test Platform, The 17th VLSI Design/CAD Symposium, 2006.
  113. K.J. Lee, Tong-Yu Hsieh and Melvin A. Breuer, A Novel Test Methodology Based on Error-Rate to Support Error-Tolerance, International Test Conference, pp. 1136-1144, 2005.
  114. Sheng-Chih Shen, Hung-Min Hsu, Yi-Wei Chang and K.J. Lee, "A High Speed BIST Architecture for DDR-SDRAM Testing," in Proc. IEEE International Workshop on Memory Technology, Design and Testing, pp. 52-57, 2005.
  115. K.-J. Lee, C.-Y. Chu, Y.-T. Hong, “An embedded processor based SOC test platform,” IEEE Int’l Symp. on Circuits and Systems, pp. 2983-2986, 2005.
  116. W.-L. Wang and K.-J. Lee, “A complete memory address generator for scan based march algorithms,” IEEE Int’l Workshop on Memory Technology, Design& Test, pp. 83-88, 2005.
  117. T.-P. Wang, C.-Y. Tsai, M.-D. Shieh and K.-J. Lee, “Efficient test scheduling for hierarchical core based design,” IEEE Int’l Symp. on VLSI Design, Automation, Test, pp. 200-203, 2005.
  118. Tong-Yu Hsieh and K.J. Lee, Error-Rate Estimation for Error-Tolerance and Yield Improvement, The 16th VLSI Design/CAD Symposium, 2005.
  119. Shen-Chih Shen, Hung-Min Hsu, Yi-Wei Chang and K.J. Lee, High-Speed Built-In Self-Test for Double Data Rate Memory, The 16th VLSI Design/CAD Symposium, 2005.
  120. Chih-Haur Huang, Soon-Jyh Chang and K.J. Lee, Design of High-Resolution Pipelined Analog-to-Digital Converters using Multiple-Phase Capacitor-Splitting Feedback Interchange Technique, 2004 Asian Pacific Conf. on Circuits and Systems, pp.625-628, 2004.
  121. Sheng-Chih Shen, You-Chung Lin, Ming-Der Shieh, and K.J. Lee, Efficient Testing and Design-for-Testability Schemes for Multimedia Cores: A Case Study on DCT Circuits, 2004 Asian Pacific Conf. on Circuits and Systems, pp. 177-180, 2004.
  122. Chih-Haur Huang, K.J. Lee and Soon-Jyh Chang, A Low-Cost Diagnosis Methodology for Pipelined A/D Converters, 14th Asian Test Symposium, pp. 296-301, 2004.
  123. K.J. Lee, Shaing-Jer Hsu and Chia-Ming Ho, Test Power Reduction with Multiple Capture Orders, 14th Asian Test Symposium, 2004, pp. 26-31, 2004.
  124. Min-Chien Chen, K.J. Lee and Tsuei-Ling Hsieh. A Hybrid Functional Testing Method for Embedded Processor Cores. The 15th VLSI DESIGN/CAD Symposium, 2004.
  125. Chih-Haur Huang, Soon-Jyh Chang and K.J. Lee. A 12-bit 40MS/s Pipelined A/D Converter using Multiple-Phase Capacitor-Splitting Feedback Interchange Technique.The 15th VLSI DESIGN/CAD Symposium, 2004.
  126. K.J. Lee, Yao-Ching Chiang, Yu-Ting Hung, Jyh-Herng Wang, and Hsiao-Ping Lin. Advanced Scan Architecture for Test Time and Test Volume Reductions. The 15th VLSI DESIGN/CAD Symposium, 2004.
  127. K.J. Lee, Soon-Jyh Chang and Ruei-Shiuan Tzeng. A Sigma-Delta modulation based BIST for A/D Converters. In Proc. 14th Asian Test Symposium, pp. 124-127, 2003.
  128. K.J. Lee, Soon-Jyh Chang and Ruei-Shiuan Tzeng. A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. The 14th VLSI DESIGN/CAD Symposium, 2003.
  129. K.J. Lee and Jih-Jeen Chen. Reducing test application time and power dissipation for scan-based testing via multiple clock disabling. In Proc. 12th Asian Test Symposium, pp. 338-343, 2002.
  130. Wei-Lun Wang and K.J. Lee. A programmable data background generator for march-based memory testing. Asia-Pacific Conference on ASIC, pp. 347-350, 2002.
  131. Jih-Jeen Chen and K.J. Lee. Test scheduling & clock disabling for test time and power reduction. The 13th VLSI DESIGN/CAD Symposium, pp. 456-459, 2002.
  132. Yu-Ting Hung and K.J. Lee. An embedded-processor-driven platform for SOC testing. The 13th VLSI DESIGN/CAD Symposium, pp. 178-181, 2002.
  133. Wei-Lun Wang and K.J. Lee. Accelerated Test Pattern Generators for Mixed-Mode BIST Environments. The 10th Anniversary Compendium of Papers from Asian Test Symposium, pp. 335-340, 2001.
  134. K.J. Lee, J.J. Tang, T.C. huang and C.L. Tsai. Combination of automatic test pattern generation and built-in intermediate voltage sensing for detecting CMOS bridging faults. The 10th Anniversary Compendium of Papers from Asian Test Symposium, pp. 169-174, 2001.
  135. Tsung-Chu Huang and K.J. Lee. A token structure for low power scan design. In Proc. 32nd Intl’ Test Conference, pp. 660-669, 2001.
  136. Tsung-Chu Huang and K.J. Lee. A low-power LFSR architecture. In Proc. 10th Asian Test Symposium, Japan, pp. 470, 2001.
  137. K.J. Lee, Jih-Jeen Chen and Tsung-Chu Huang. Test power reduction for scan-based design. The 12th VLSI DESIGN/CAD Symposium., Paper A3-10, 2001.
  138. Wei-Lun Wang and K.J. Lee. A universal and expandable data background generator for memory testing. The 12th VLSI DESIGN/CAD Symposium, Paper A3-7, 2001.
  139. Tsung-Chu Huang and K.J. Lee. A token structure for low power scan design. The 12th VLSI DESIGN/CAD Symposium, Paper A3-1, 2001.
  140. K.J. Lee and Cheng-I Huang. A Hierarchical Test Control Architecture for Core Based Design. The 9th Asian Test Symposium, pp. 248-253, 2000.
  141. Wei-Lun Wang and K.J. Lee. Accelerated Test Pattern Generators for Mixed-Mode BIST Environments. The 9th Asian Test Symposium, pp. 368-373, 2000.
  142. K.J. Lee, Tsung-Chu Huang, and Jih-Jeen Chen. Test power reduction for multiple scan circuits during test application. The 9th Asian Test Symposium, pp. 453-458, 2000.
  143. Yun-Che Wen and K.J. Lee. An on chip ADC test structure. In Proc. Design And Test Conference of Europe (DATE), pp. 221-225, 2000.
  144. Yun-Che Wen and K.J. Lee. Static parameters testing for A/D converters. The 11th VLSI DESIGN/CAD Symposium, pp. 417-420, 2000.
  145. Tsung-Chu Huang and K.J. Lee. Interleaving Multiple Scan Technique to Reduce Peak-Power. The 11th VLSI DESIGN/CAD Symposium, pp. 385-388, 2000.
  146. K.J. Lee and Cheng-I Huang. A hierarchical test control architecture for core based design. The 11th VLSI DESIGN/CAD Symposium, pp. 227-230, 2000.
  147. W.-B. Jone, D.-S. Huang, and K.-J. Lee, “An efficient BIST method for small buffers,” IEEE VLSI Test Symp., pp. 246-251, 1999.
  148. K.-J. Lee, C.-Y. Hwang, and Y.-K. Tsao, “AFSPG: An automatic faulty SPICE program generation system,” VLSI DESIGN/CAD Symp. pp. 187-190, 1999.
  149. T.-C. Huang and K.-J. Lee, “An input control technique for power reduction in scan circuits during test application,” IEEE Asian Test Symp., pp. 315-319, Nov. 1999.
  150. W.-L. Wang and K.-J. Lee, “A universal March pattern generator for testing embedded memory cores,” IEEE Int’l ASIC/SOC Conf. pp. 228-232, 1999.
  151. K.-J. Lee and W.-C. Wang, “A 0.5μm operational trans-conductance amplifier-capacitor filter with concurrent error detection capability,” IEEE Int'l Analog VLSI Workshop, pp. 103-108, 1999.
  152. W.-L. Wang and K.-J. Lee, “An embedded March algorithm test pattern generator for memory testing,” IEEE Int’l Symp. on VLSI Technology, Systems, and Applications. pp. 211-214, 1999.
  153. K.-J. Lee, M.-C. Huang, and I.-H. Shih, “Functional test sequence generation and compaction for cache memory,” Microprocessor Workshop. pp. 90-93, 1999.
  154. Shih-Chieh Chang, K.J. Lee, Zhong-Zhen Wu and Wen-Ben Jone. Test application time reduction by input signal aharing. In Proc. 10th VLSI DESIGN/CAD Symposium. pp. 115-118, Aug., 1999.
  155. Wei-Chiang Wang and K.J. Lee. A systematic approach to design testable gm-C filters. In Proc. 10th VLSI DESIGN/CAD Symposium, pp. 183-186, 1999.
  156. Tsung-Chu Huang and K.J. Lee. Test power reduction during scan operation via input control. In Proc. 10th VLSI DESIGN/CAD Symposium, pp. 107-110, 1999.
  157. W.B. Jone, D.C. Huang, S.C. Wu and K.J. Lee. A parallel testing method for embedded small buffers. In Proc. Microprocessor Workshop, pp. 83-89, 1999.
  158. K.J. Lee, Jih-Jeen Chen and Cheng-Hua Huang. Reducing test application time via input sharing. In Proc. Microprocessor Workshop, pp. 77-82, 1999.
  159. K.-J. Lee, J.-J. Tang, W.-Y. Du, and T.-C. Huang, “On the determination of threshold voltages for CMOS gates to facilitate test pattern generation and fault simulation,” IEEE Asian Test Symp., pp.113-118, 1998.
  160. K.-J. Lee, J.-J. Chen, and C.-H. Huang, “Using a single input to support multiple scan chains,” IEEE Int'l Conf. on Computer-Aided Design. pp. 74-78, 1998.
  161. K.J. Lee and Jing-Jong Tang, Wern-Yih Du and Tsung-Chu Huang. On the determination of threshold voltages for CMOS gates to faciliate test pattern generation and fault simulation. In Proc. 9th VLSI DESIGN/CAD Symp, pp. 173-176, 1998.
  162. K.J. Lee, Min-Cheng Huang and Ing-Heng Shih. Functional testing for cache memory. In Proc. 9th VLSI DESIGN/CAD Symposium, pp. 165-168, 1998.
  163. Tsung-Chu Huang and K.J. Lee. A new built-in current sensor for deep submicron CMOS ICs. In Proc. 9th VLSI DESIGN/CAD Symposium, pp. 141-144, 1998.
  164. K.-J. Lee and T.-C. Huang, “Bulk-driven technique for current testing,” IEEE Int'l Conf. on Chip Technology. pp. 158-165, 1998.
  165. T.-C. Huang and M.-C. Huang, K.-J. Lee, “Built-in current sensor designs based on the bulk-driven techniques,” IEEE Asian Test Symp. pp. 384-388, 1997.
  166. T.-C. Huang, M.-C. Huang, and K.-J. Lee, “A high-speed low-voltage built-in current sensor,” IEEE Int'l Workshop on IDDQ Testing, pp. 90-94, 1997.
  167. K.J. Lee, Tsung-Chu Huang and Min-Cheng Huang. A low-voltage built-in current sensing technique. In Proc. 8th VLSI DESIGN/CAD Symposium, pp. 51-54, 1997.
  168. C.-L. Lee, J.-Y. Jou, C.-S. Lin, J.-E. Chen, C.-W. Wu, K.-J. Lee, and C.-C. Su, “A joint project to develop a VLSI testing and design-for-testability course for universities in Taiwan,” IEEE Int’l Conf. on Engineering Education, pp. 43-53, 1997.
  169. K.-J. Lee, J.-J. Tang, T.-C. Huang, and C.-L. Tsai, “Combination of automatic test pattern generation and built-in intermediate voltage sensing for detecting CMOS bridging faults,” IEEE Asian Test Symp., pp. 100-105, Nov. 1996.
  170. K.-J. Lee and J.-J. Tang, “Two modeling techniques for CMOS circuits to enhance test generation and fault simulation for bridging faults,” IEEE Asian Test Symp., pp. 165-170, Nov. 1996.
  171. K.S. Huang and K.-J. Lee, “A current-mode testable and diagnosable design of OTA-C filters,” HD-Media Workshop, pp. A5-5/25-30, Nov. 1996.
  172. K.J. Lee, J.J. Tang, T.C. Huang and C.L. Tsai. Analysis of resistive inter-gate bridging faults In CMOS circuits. In Proc.7th VLSI DESIGN/CAD Symposium, pp.73-76, Aug. 1996.
  173. T.-P. Lee, K.-J. Lee, and R.-C. Wen, “System level testing for mixed-mode circuits,” HD-Media Workshop, pp. PO1.14-PO1.19, Nov. 1995.
  174. J.-L. Kuo and K.-J. Lee, “A novel fault tolerant architecture for video filters,” HD-Media Workshop, pp. PO1.20-PO1.25, Nov. 1995.
  175. J.J. Tang, K.J. Lee and B.D. Liu. Analysis of resistive inter-gate bridging faults In CMOS circuits. In Proc. 6th VLSI DESIGN/CAD Symposium, pp. 93-96, Aug. 1995.
  176. K.J. Lee, J.J. Tang and C.Y. Chen. A simple and effective design of built-in intermediate voltage sensors. In Proc. 6th VLSI DESIGN/CAD Symposium, pp. 43-46, Aug. 1995.
  177. K.J.Lee, J.J. Tang and Kou-Sheng Huang. A built-in current sensor based on current-mode and dual-power design. In Proc. 6th VLSI DESIGN/CAD Symposium, pp. 26-29, Aug. 1995.
  178. K.-J. Lee, S.-Y. Jeng, and T.-P. Lee, “A new architecture for analog boundary scan,” IEEE Int'l Symp. on Circuits and Systems, pp. 409-412, May 1995.
  179. J.-J. Tang, B.-D. Liu and K.-J. Lee, “An IDDQ fault model to facilitate the design of built-in current sensors (BICSs),” IEEE Int'l Symp. on Circuits and Systems, pp. 393-396, May 1995.
  180. J.-J. Tang, K.-J. Lee, and B.-D. Liu, “Built-in intermediate voltage testing for CMOS circuits,” IEEE European Design and Test Conf., pp. 372-376, Mar. 1995.
  181. C.-H. Kuo and K.-J. Lee, “Concurrent error detection, diagnosis and fault tolerance for operational trans-conductance amplifier capacitor based video filters,” HD-Media Workshop, pp.PO2.1-PO2.6, Oct. 1994. (Best paper award)
  182. K.J. Lee, J.J. Tang and B.D. Liu. Built-in intermediate voltage testing for CMOS circuits. In Proc. 5th VLSI DESIGN/CAD Symposium, pp. 245-250, Aug. 1994.
  183. K.J. Lee and Cheng-Hsuing Kuo. Concurrent error detection, diagnosis and fault tolerance for switched-capacitor filters. In Proc. 5th VLSI DESIGN/CAD Symposium, pp.205-210, Aug. 1994.
  184. K.-J. Lee, M.-H. Lu, and J.-F. Wang, “A systematic method to classify scan cells,” IEEE Asian Test Symp., pp.219-224, Nov. 1993.
  185. J.-J. Tang, K.-J. Lee, and B.-D. Liu, “A real time IDDQ testing scheme using current conveyor technique,” Int'l Symp. on IC Technology, Systems & Applications, pp.348-352, Sep. 1993.
  186. J.-J. Tang, K.-J. Lee, and B.-D. Liu, “Maximum fault diagnosis resolution for programmable logic array,” Int'l Symp. on IC Technology, Systems & Applications, pp.100-104, Sep. 1993.
  187. J. J. Tang, K.J. Lee, and B.D. Liu. "A new current sensing technique for IDDQ testing." In Proc. 4th VLSI DESIGN/CAD Workshop, pp.166-170, Aug. 1993.
  188. J.-J. Tang, K.-J. Lee, and B.-D. Liu, “A new representation for programmable logic arrays to facilitate testing and logic design,” IEEE TENCON'93, pp.561-564, Oct. 1993
  189. W.-L. Wang, K.-J. Lee, and J.-F. Wang, “Design of real time fault detectors using linear feedback shift registers,” IEEE Int'l Electron Devices & Material Symp., pp.193-195, Nov. 1992.
  190. W.-L. Wang, J.-F. Wang, and K.-J. Lee, “A fast testing method for sequential circuits at the state transition level,” IEEE Int'l Test Conf., pp. 514-519, Sep. 1992.
  191. K.-J. Lee, C.A. Njinda, and M.A. Breuer, “SWiTEST: A switch level test generation system for CMOS combinational circuits,” IEEE Design Automation Conf., pp. 26-29, Jun. 1992.
  192. K.-J. Lee and M.A. Breuer, “Constraints for using IDDQ testing to detect CMOS bridging faults,” IEEE VLSI Test Symp., pp. 303-308, May 1991.
  193. K.-J. Lee and M.A. Breuer, “A new method for assigning signal flow directions to MOS transistors” IEEE Int'l Conf. on Computer-Aided Design, pp. 492-495, Nov. 1990.
  194. K.-J. Lee and M.A. Breuer, “On the charge sharing problem in CMOS stuck-open fault testing,” IEEE Int’l Test Conf., pp. 417-426, Sep. 1990.
  195. K.-J. Lee and M.A. Breuer, “On detecting single and multiple bridging faults In CMOS circuits using the current supply monitoring method,” IEEE Int’l Symp. on Circuits and Systems, pp. 5-8, May 1990.
  196. K.-J. Lee and M.A. Breuer, “A universal test sequence for CMOS scan registers,” IEEE Custom Integrated Circuit Conf., pp. 28.5.1-28.5.4, May 1990
  197. M.A. Breuer, R. Gupta, R. Gupta, K.-J. Lee, and J.C. Lien, “Knowledge-based systems for test and diagnosis,” IIFIP Workshop on KBS for Test & Diagnosis, Grenoble, France, pp. 3-28, Sep. 1988.
專利
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less
  1. 李昆忠，陳郁翔，”具掃描鍊架構與邏輯單元矩陣之測試晶片架構及其診斷方法” ROC Invention patent no. I734420, July 21, 2021.
  2. 李昆忠，吳家騏，郭蔓萱，”測試電路之動態密鑰防禦架構與方法” ROC Invention patent no. I725900, May 11, 2021.
  3. K.-J. Lee, J.-Z. Chen, “Test Decompressor and Test Method Thereof,” 10,324,130，Jun.18, 2019, USA.
  4. K.-J. Lee, P.-H. Tang, “Integrated Circuit Automatic Test System and Integrated Circuit Automatic Test Method Storing Test Data in Scan Chains,” 10,324,129, Jnu. 18, 2019, US.
  5. K.-J. Lee, J.-Z. Chen, 一種測試資料之解壓縮器及其測試方法, I612317, 2018/1/21, ROC.
  6. K.-J. Lee, C.-H. Wu, W.-C. Lien, H Lin, Y Liu, J Chen, Defect Diagnosis, invention patent number 9,766,286, 2017/9/19, USA.
  7. K.-J. Lee, P.-H. Tang, An on-chip self-test architecture with test patterns recorded in scan chains, I609190, 2017/12/21, ROC.
  8. K.-J. Lee, and L.-J. Lee, “Three-dimensional IC test system and its method,” invention patent number 1530701, 2016/4/20, ROC.
  9. S. J. Chang, G.-Y. Huang, K.-J. Lee, W.-Y. Su, C.-H. Chen, L.-Y. Chiou, C.-H. Kuo, C.-H. Tsai, and C.-M. Lin, “Multi-point temperature sensing method for integrated circuit chips and system of the same,” invention patent number 9,448,122, 2016/9/20, USA.
  10. K.J. Lee and J.J. Tang. Intermediate voltage sensors for CMOS circuits. ROC Invention number 077093, period: Feb.11, 1996 -- July 16, 2015.
  11. K.J. Lee and J.J. Tang. Intermediate voltage sensor for CMOS circuits. USA Patent number 5,631,575, Date of Patent: May 20, 1997.
  12. K.J. Lee and J.J. Tang 5,808,476 Built-in current sensor for IDDQ monitoring. Built-in current sensor for IDDQ monitoring. USA patent number 5,808,476, Date of Patent: Sep. 15, 1998.
  13. K.J. Lee and J.J. Tang. A built-in current sensor based on current mode technique. ROC patent number 111,969., period: Feb. 11, 2000 – Oct. 19, 2015.
  14. K.J. Lee, J.J. Chen and C.H. Huang. Test architecture and test generation method for using one data input to support multiple scan chains. ROC patent number 118,268, period: July 21, 2000 – Jan. 28, 2019.
  15. K.J. Lee, J.Y. Wu and W.B. Jone. Built-in Self Test for Multiple Memories in a Chip. ROC invention patent number 123,572, period: Nov. 11, 2000 – Jun. 22, 2018.
  16. K.J. Lee, T.P. Lee and S.Y. Cheng. An analog boundary scan design. ROC invention patent number 125,758, period: Dec. 1, 2000 – Feb. 29, 2016.
  17. K.J. Lee, J.Y. Wu and W.B. Jone. Built-in Self Test for Multiple Memories in a Chip. USA invention patent 6,360,342, Date of Patent: Mar. 19, 2002.
  18. K.J. Lee, J.J. Chen and C.H. Huang. Test architecture and test generation method for using one data input to support multiple scan chains. USA invention patent 7159161, date of patent: Jan. 2, 2007 – Aug. 17, 2021.
  19. C.M. Huang, C.C. Yang, J.Y. Jou, K.J. Lee, and L.D. Van. Multiple-Project System-On-Chip and its Method.?USA Invention Patent 7,571,414, date of patent: Aug. 4, 2009.
  20. C.M. Huang, C.C. Yang, J.Y. Jou, K.J. Lee, and L.D. Van. Multiple-Project System-On-Chip and its Method.?ROC Invention Patent 306,211, date of patent: Feb. 11, 2009 - May 18, 2026.
  21. K.-J. Lee, and Jia-Wei Jhou, “Debugging control system using inside-core event as trigger condition and method of the same,” invention patent number 8,892,973, 2014/3/13, USA.
  22. K.-J. Lee, and Jia-Wei Jhou, “Debugging control system using inside-core event as trigger condition and method of the same,” invention patent number I472912, 2015/2/11, ROC.
  23. S. J. Chang, G.-Y. Huang, K.-J. Lee, W.-Y. Su, C.-H. Chen, L.-Y. Chiou, C.-H. Kuo, C.-H. Tsai, and C.-M. Lin, “Method for sensing multi-point temperatures applied to integrated circuit chips and system for the same,” invention patent number I489093, 2015/6/21, ROC.
  24. K.-J. Lee, and L.-J. Lee, “Three-dimensional IC test system and its method,” invention patent number 1530701, 2016/4/20, ROC.
  25. S. J. Chang, G.-Y. Huang, K.-J. Lee, W.-Y. Su, C.-H. Chen, L.-Y. Chiou, C.-H. Kuo, C.-H. Tsai, and C.-M. Lin, “Multi-point temperature sensing method for integrated circuit chips and system of the same,” invention patent number 9,448,122, 2016/9/20, USA.
  26. K.-J. Lee, C.-H. Wu, W.-C. Lien, H Lin, Y Liu, J Chen, Defect Diagnosis, US Patent application.
其他
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less
  1. Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba,VLSI TEST PRINCIPLES AND ARCHITECHTURES,Ch6 Test Compression(p341-p396),MORGAN KAUFMANN,2006, ISBN:978-0-12-370597-6
  2. K.J. Lee. Switch level test generation for CMOS circuits. PhD Dissertation, Univ. of Southern California, Los Angeles, August 1991.
研究計劃
  1. 先進製程技術之測試晶片設計及標準元件之測試與診斷流程開發, supported by Minitary of Science and Technology (MOST)(2022/08~2024/07)
  2. 3DIC Testability and Diagnosability enhancement for Heterogenous chips(2023/03~2025/02)
  3. 旁通道攻擊自動化偵測與防禦計畫, supported by 財團法人資訊工業策進會.(2022/04~2022/11)
  4. Research project, “High-security and low-power design & test technologies for SOC in IoT edge nodek,” supported by Qualcomm Co., USA. (2022/07~2023/06)
  5. Test Compression Technologies, supported by 群聯電子公司(2021/07~2022/07)
  6. Research project, “AI and PUF-based Low-power and High-Security Technologies for IoT Chips and Network,” supported by Qualcomm Co., USA.(2020/06~2022/05)
  7. 物聯網安全性設計應用於智慧養殖影像資料傳輸之評估 supported by 海盛科技(2020/01~2020/12)
  8. Research on EDT Compression Techniques, supported by Mentor Graphics, USA.(2020/01~2020/12)
  9. Research collaboration with Qualcomm, supported by Qualcomm Co., USA.(2019/06~2019/12)
  10. Research on EDT Compression Techniques, supported by Mentor Graphics, USA.(2019/01~2019/12)
  11. Research on Deep Learning Techniques, supported by Mentor Graphics, USA.(2018/08~2018/12:)
  12. 先進製程技術之測試晶片設計及標準元件之測試與診斷流程開發(2022-2024)
  13. 高安全性物聯網裝置之開發平台 (2022-2024)
  14. 智慧終端半導體製程與晶片系統研發專案計畫(半導體射月計畫)(2018-2022)
  15. 高壓縮率廣播掃描壓縮技術以及將測試資料儲存於掃描鍊之自我測試架構(2017-2018)
  16. 適用於多種實際錯誤模型之測試與診斷向量產生方法及其完整流程之開發(2017-2018)
  17. 車用電子之獨立式測試系統暨測試架構防駭安全技術(2016-2017)
  18. 掃描式響應回授測試技術之研發及應用(2013-2016)
  19. 考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法-總計畫暨子計畫五:三維晶片除錯架構與方法之研發(2013-2016)
  20. 智慧電子國家型科技計畫研究發展及推動規劃(2013-2014)
  21. 3D IC系統晶片測試平台之研發與應用(二) 國科會(2013-2014)
  22. 針對OpenCL平台金鑰系統技術之研發與應用 國科會(2013-2014)
  23. 3D IC系統晶片測試平台之研發與應用(一) 國科會(2012-2013)
  24. 系統晶片除錯平台之研發 國科會(2011-2012)
  25. 邏輯電路內建自我回授測試技術之研發及應用 (2011-2013)
  26. 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發-總計畫(1/3) 國科會 (2010-2011)
  27. 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發-子計畫(八) 國科會 (2010-2011)
  28. 輸出選擇響應壓縮技術之研發及應用 國科會 (2008-2011)
  29. 電子系統階層設計技術開發及其在多格式系統晶片之應用 (總計畫) (2007-2010)
  30. 系統晶片系統測試平台之設計與自動化-總計畫 國科會 (2004-2007)
  31. 系統晶片系統測試平台之設計與自動化-子計畫(四) 國科會 (2004-2007)
  32. 前瞻性掃瞄測試技術及架構之研發 國科會 (2004-2007)
  33. 單晶片系統之測試架構，測試排程及其自動產生(二) 國科會 (2003-2004)
  34. 超大型積體電路低功率測試方法之研究(二) 國科會 (2003-2004)
  35. 單晶片系統之測試架構，測試排程及其自動產生(一) 國科會 (2002-2003)
  36. 超大型積體電路低功率測試方法之研究(一) 國科會 (2002-2003)
  37. 單晶片系統測試與可測性設計(三) 國科會 (2000-2001)
  38. 單晶片系統測試與可測性設計(二) 國科會 (1999-2000)
  39. 半導體記憶體之測試研究(三) 國科會 (1999-2000)
  40. 半導體記憶體之測試研究(二) 國科會 (1998-1999)
  41. 單晶片系統測試及可測性設計(一) 國科會 (1998-1999)
  42. 半導體記憶體之測試研究(一) 國科會(1997-2000)
  43. 互動電視之介面控制與電源管理系統 國科會(1996-1997)
  44. 積體電路測試推動計畫之發展 教育部(1996-1997)
  45. 個人數位助理之測試 國科會(1995-1997)
  46. 具自我測試功能之HDTV類比電路 國科會(1994-1996)
  47. 針對CMOS non-stuck-at faults 產生測試向量及設計硬體感測器 國科會(1994-1995)
  48. CMOS電晶體之訊號流向分配研究 國科會(1992-1993)
  49. 先進製程下針對電路缺陷進行分析.診斷及修復 台積電(2015-2016)
  50. Sequential-Events Checking 技術轉移至思爾芯科技公司(2015)
  51. Event Trigger Logic技術轉移至思爾芯科技公司(2014)
  52. 針對行動裝置之測試平台研發 工研院(2014)
  53. Efficient diagnosis methodology and test architectures for physical failure analysis and yield ramping. 2D/3DIC test vehicles. 台積電(2012-2014)
  54. Effective AC-Scan Diagnosis for Successful Physical Failure Analysis 之技術開發 台積電 (2010-2011)  
  55. 高階網狀互連網路模擬分析平台 工研院 (2010)
  56. 測試架構與硬體除錯平台 創意電子 (2009-2011)
  57. 應用於PAC II之電子系統層級模擬平台  工研院系統晶片研究中心 (2008)
  58.  H.264 Encoder Un-timed ESL SystemC Model 之技術開發  思源科技 (2008)
  59. 系統晶片測試架構與測試整合之研究  工研院電腦與通訊工業研究所(2004)
  60. 系統晶片之測試與可測試設計  工研院電腦與通訊工業研究所(2003)
  61. 單晶片系統之低成本測試技術研發  智原科技公司(2003)
  62. 系統晶片之可測試設計研究  工研院電腦與通訊工業研究所(2002)
  63. 單晶片系統之低功率測試技術研發 智原科技公司(2002)
  64. 系統晶片之可測試設計自動化研究 工研院電腦與通訊工業研究所(2001)
  65. 單晶片系統之測試技術研發 華騰科技股份有限公司(2000-2001)
  66. 單晶片系統測試方法與研究  工研院(1999-2000)
  67. 板件電路模擬之元件故障模型之研究  經濟部資策會(1998-1999)
開授課程
113學年上學期
112學年下學期
112學年上學期
111學年上學期
111學年下學期
109學年上學期
109學年下學期
108學年上學期
108學年下學期
107學年上學期
107學年下學期
指導學生
本學年度 實驗室成員
碩士班
溫隆賢
陳冠融
陳稟文
李承鴻
陳家諧
彭冠穎
黃義程
簡君翰
鍾承恩
李其曄
朱宥學
林弘翊
已畢業學生
博士
連唯証   張欽堯   謝東佑   陳繼展   黃宗柱   王維倫   溫昀哲   唐經洲   吳政鴻
碩士
81
呂明圜
82
王志男
83
鄭昇益   郭政雄
84
郭建隆   李天寶   蔡政良
85
謝雨蒼   黃國聲   陳俊裕
86
賴哲恆   林哲儀   戴自強
87
吳俊源   黃敏政   李耿維   黃正華   杜文毅
88
王煒強   莊佳恩   莊凱文   石穎衡
89
胡文軒   徐培根   黃正儀
90
曾裕淵   陳俊嘉   莊賀傑   陳朝義
91
許哲綸   洪忻煒   洪郁庭   曾瑞鉉   曾南欣
92
陳旻謙   楊家凱   徐祥哲   張浚恆   林友中
93
謝翠玲   蔣耀慶   張逸偉   黃志豪   朱家頤   方建偉
94
廖文聰   吳明隆   何嘉銘   陳家揚   陳瑞嶸   沈聖智
95
郭明典   黃文成   黃琨懿   許宏銘
96
顏成偉   王嘉德   尤建智   邱政斌
97
程育賢   洪銘澤   蕭智元   陳紹元   吳育樺   梁思遠
98
姚奇宏   張怡均   蔡振宗   謝仕興
99
戴士翔   林郁傑   簡士勛   方俊翰   陳伊柔
100
張源   黃文鴻   周佳緯   洪偉倫
101
王奕達   蕭崇閔   陳信辰   簡新恩   張鈞智
102
李良哲   許峻嘉   林倬民
103
留國凱   楊驥   吳承融   王聖澤   陳鎮宗
104
郭興邦   唐品豪   許文軒   李信徵
105
吳俊緯   陳昶聞   洪碩聯   林盛霖   葉金村
106
吳家騏   陳柏任
107
商朝鈞   郭蔓萱   龔宜成
108
侯宗佑   胡峻誠   劉晴安   蔡豐駿   盧煜勝   賴志維   陳郁翔
109
葉崇孝   胡峻銘   呂正耀   紀閎耀   許家銘
110
饒梓俊   黃毓斌   林脩甯   葉仕鈞   鄭詩璇
111
黃柏豪   黃柏華   陳翔宇   陳彥甫   葉川瑜
112
林鈺筌   蘇靖凱   陳東逸
特殊榮譽
  1. 2023: 旺宏金矽奬優勝奬
  2. 2022: 2022 Best paper award, Journal of Electronic Testing: Theory & Application.
  3. 2022: 2022 Best paper award, IEEE Asian Test Symposium
  4. 2022: Best paper award candidate, Int’l Test Conf. in Asia, 2022
  5. 2022: Program Chair, IEEE International Test Conference
  6. 2021~present: Steering Committee member, IEEE International Test Conference
  7. 2021: 指導學生黃柏華、黃柏豪、陳翔宇參加LINE Chatbot 對話機器人設計大賽冠軍 ( 官方公布參賽隊伍數:  60).
  8. 2021: 指導學生黃柏華、陳翔宇參加中華電信5G創新應用大賽亞軍 (官方公布參賽隊伍數: 225).
  9. 2021: Best paper award, VLSI Test Technology Workshop
  10. 2021: Steering Committee member, IEEE International Test Conference
  11. 2021: Vice Program Chair, IEEE International Test Conference.
  12. 2020: Nomination & Appointments chair, IEEE Tainan Section
  13. 2020: 指導學生胡峻銘獲聯詠科技碩士班奬學金
  14. 2020: 指導學生呂正耀、黃毓斌獲TSRI IC設計競賽佳作
  15. 2019: 指導學生劉晴安獲2019聯發科技「智在家鄉」競賽首獎 ( 官方公布參賽隊伍數: 360)
  16. 2019: 科技部未來科技突破奬
  17. 2019~2020: IEEE International Test Conference (ITC), track chair.
  18. 2019: Best paper award, VLSI Test Technology Workshop
  19. 2017: Outstanding Technical Achievement Award, IEEE Tainan Section
  20. 2017: Best paper award, IEEE International Test Conference in Asia
  21. 2017:指導學生洪碩聯獲亞洲測試會議最佳論文獎
  22. 2017: IEEE International Test Conference in Asia 大會主席
  23. 2016: Best paper award, VLSI/CAD Symposium
  24. 2016: 獲選為IEEE Fellow 2017 "For contributions to low-cost testing of digital VLSI circuits"
  25. 2016:論文"An Efficient Test Pattern Generation Method for Cell-Internal Faults”榮獲全國 VLSI DESIGN/CAD Symposium 最佳論文奬
  26. 2015: Supervising, Best PhD thesis award, Taiwan Institute of Electrical & Electronic Engineering (TIEEE)
  27. 2015: Supervising, Best PhD thesis award, IEEE Asian Test Symposium
  28. 2015:論文"An efficient diagnosis pattern generation method for stuck-at-faults with high test compaction”榮獲全國 VLSI DESIGN/CAD Symposium 最佳論文奬
  29. 2015: Supervising, Best PhD thesis award, Taiwan IC Design Society
  30. 2015:論文"Diagnosis pattern generation to distinguish transition delay faults and transistor stuck-open faults”榮獲VLSI Test Technology Workshop 最佳論文奬
  31. 2015: 指導學生吳政鴻獲台積電博士班奬學金
  32. 2014-2016: 亞洲測試會議指導委員會主席
  33. 2014 全國VLSI Design/CAD 會議最佳展示奬
  34. 2014 全國VLSI Design/CAD 會議最佳海報奬
  35. 2014: 指導學生吳政鴻獲台積電博士班奬學金
  36. 2013-2014: 智慧電子國家型計畫科技部工程司召集人
  37. 2013: IEEE Workshop on RTL Testing 大會主席
  38. 2013: 第十三屆旺宏金矽獎金獎
  39. 2013: 李昆忠教授主持之「具易測試及除錯特性之智慧型低功率多核心系統之設計技術。研發:從電子系統層級至矽晶片層級」之整合型計劃 (2010/8-2013/7) 榮獲102年度 科技部整合型計劃「績優計畫獎」
  40. 2012: 指導學生連唯証獲聯發科技奬學金
  41. 2012 VLSI Test Technology Workshop 最佳論文奬
  42. 2011: NSOC 國家型計畫專案召集人
  43. 2011: VLSI-CAD Symposium 最佳論文奬
  44. 2010-2013: 亞洲測試會議指導委員會副主席
  45. 2010: IEEE International Symposium on VLSI-DAT Symposium大會共同主席
  46. 2009: IEEE International Symposium on VLSI-DAT會議議程主席
  47. 2009: IEEE International Symposium on Circuits & Systems會議課程主席
  48. 2008: VLSI Test Technology Workshop大會主席
  49. 2008-2010: 台灣積體電路設計學會理事長
  50. 2008-2010: 國立成功大學晶片系統研發中心主任 Director, SoC Research Center
  51. 2007: 李昆忠教授主持之「晶片系統測試平台之設計與自動化」之整合型計劃 (2004-2007)。榮獲96年度國科會 整合型計劃「績優計畫獎」，為當年度全國唯一獲此殊榮之晶片系統國家型科技計畫.
  52. 2007: 國家實驗研究院 傑出科技貢獻獎 科技服務類(團體) 多計畫系統單晶片設計服務 雪山獎.
  53. 2006-2008：台灣系統晶片設計推動聯盟ESL工作小組副召集人
  54. 2005/8-2006/12: VLSI教改計畫ESL課程開發計畫主持人
  55. 2005-2006: IEEE Circuits & Systems Tainan Chapter Chairman
  56. 2005: Founder, IEEE Tainan Chapter, Circuits & Systems Society
  57. 2004-2006: 台灣積體電路設計學會副理事長
  58. 2004: 特邀主編 (Guest Editor). Int'l Journal of Electrical Engineering, Special Issue on APCCAS 2004. Feb. 2006. 
  59. 2004: IEEE 亞洲測試會議會議大會主席.
  60. 2004: VLSI教改計畫S&IP聯盟召集人
  61. 2002-2003: VLSI教改計畫DIP聯盟執行秘書.
  62. 2002~2015: 國科會研究計畫獎助.
  63. 2002: 全國VLSI/CAD Symposium大會主席.
  64. 2002: 國科會大專學生研究創作奬.
  65. 2002: 特邀主編 (Guest Editor).Journal of Electronic Testing: Theory and Applications 、 (JETTA), Special Issue on ATS 2000, February, 2002.
  66. 2001: IEEE Computer Society, Asian Test Symposium, Certificate of Appreciation.
  67. 2000: IEEE亞洲測試會議議程主席
  68. 2000: 特邀主編 (Guest Editor).Journal of Information Science & Engineering (JISE), Special Issue on VLSI Testing, October, 2000.
  69. 1999: 國家IC設計大賽 ，榮獲團隊第四名
  70. 1999: 教育部VLSI與系統設計教育改進計劃 特優
  71. 1994: HD-Media Technology and Applications Workshop, Best paper award.
  72. 1991-2002: 國科會甲種研究獎
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